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ICS950104YFT Datasheet

  • ICS950104YFT

  • Programmable System Clock Chip for PIII Processor

  • 223.72KB

  • 19頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS950104
Advance Information
Programmable System Clock Chip for PIII鈩?/div>
Processor
Recommended Application:
SIS630ST style chipset
Output Features:
鈥?/div>
1 - CPU clocks @ 2.5V
鈥?/div>
1 - Pair of differential CPU clocks @ 3.3V
鈥?/div>
9 - SDRAM @ 3.3V
鈥?/div>
7 - PCI @3.3V
鈥?/div>
1 - 48MHz, @3.3V
鈥?/div>
1 - 24/48MHz @ 3.3V
鈥?/div>
3 - REF @3.3V, (selectable strength) through I
2
C
Features:
鈥?/div>
Programmable ouput frequency
鈥?/div>
Programmable ouput rise/fall time
鈥?/div>
Programmable CPU, SDRAM, and PCI skew
鈥?/div>
Real time system reset output
鈥?/div>
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread percentage
鈥?/div>
Watchdog timer technology to reset system
if over-clocking causes malfunction
鈥?/div>
Uses external 14.318MHz crystal
Skew Specifications:
鈥?/div>
CPU - CPU: <250ps
鈥?/div>
PCI - PCI: <500ps
鈥?/div>
SDRAM - SDRAM: <250ps
鈥?/div>
CPU - SDRAM:<350ps
鈥?/div>
CPU - PCI: <3ns
Pin Configuration
CPUCLKC0
CPUCLKT0
VDDCPU
GND
AVDD
X1
X2
**FS0/REF0
VDDREF
**FS1/REF1
REF2
GND
*FS2/PCICLK_F
PCICLK0
PCICLK1
PCICLK2
GND
VDDPCI
PCICLK3
PCICLK4
PCICLK5
AVDD48
**MULTSEL/24_48MHz
**FS3/48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
GND
IREF
GND
CPUCLK
VDDL
SDATA
SDRAM_STOP#*
SDRAM0
SDRAM1
SDRAM2
SDRAM3
VDD
GND
SDRAM4
SDRAM5
SDRAM6
SDRAM7
GND
VDD
PCI_STOP#*
CPU_STOP#*
PD#/Vtt_PWRGD#*
SCLK
GND
48-Pin 300mil SSOP
Notes:
REF0 can be 1X or 2X strength controlled by I
2
C.
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down of 120K to GND
Functionality
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
3
REF(2:0)
CPU
DIVDER
Stop
CPUCLKT0
CPUCLKC0
CPUCLK
SDATA
SCLK
FS(3:0)
PD#
PCI_STOP#
CPU_STOP#
MODE
MULTSEL
Control
Logic
SDRAM
DIVDER
Stop
10
SDRAM (9:0)
PCI
DIVDER
Stop
6
PCICLK (5:0)
PCICLK_F
Config.
Reg.
CPU
(MHz)
66.6
100.0
150.0
133.3
66.8
100.0
100.0
133.3
66.8
97.0
70.0
95.0
95.0
112.0
97.0
96.2
ICS950104
SDRAM
(MHz)
100.0
100.0
100.0
100.0
133.6
133.3
150.0
133.3
66.8
97.0
105.0
95.0
126.7
112.0
129.3
96.2
PCICLK
(MHz)
33.3
33.3
37.5
33.3
33.4
33.3
37.5
33.3
33.4
32.3
35.0
31.7
31.7
37.3
32.2
32.1
950104 Rev - 09/11/01
Third party brands and names are the property of their respective owners.
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.

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