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ICS94228YFLF-T Datasheet

  • ICS94228YFLF-T

  • Programmable System Clock Chip for AMD - K7⑩ processor

  • 136.30KB

  • 17頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS94228
Programmable System Clock Chip for AMD - K7鈩?processor
Recommended Application:
VIA KT266 style chipset
Output Features:
鈥?/div>
1 - Differential pair open drain CPU clocks @ 2.7V
鈥?/div>
1 - Differential pair push-pull CPU clocks @ 2.5V
鈥?/div>
11 - PCI including 1 free running and 1 early @ 3.3V
鈥?/div>
1 - 48MHz, @ 3.3V fixed
鈥?/div>
1 - 24/48MHz @ 3.3V
鈥?/div>
3 - REF @ 3.3V, 14.318MHz.
Features:
鈥?/div>
Programmable output frequency.
鈥?/div>
Programmable output rise/fall time.
鈥?/div>
Programmable slew and skew control for CPUCLK,
PCICLK, AGP, REF, 48MHz and 24_48MHz.
鈥?/div>
Real time system reset output.
鈥?/div>
Spread spectrum for EMI control typically
by 7dB to 8dB, with programmable spread
percentage.
鈥?/div>
Watchdog timer technology to reset system
if over-clocking causes malfunction.
鈥?/div>
Uses external 14.318MHz crystal.
Skew Specifications:
鈥?/div>
CPU - CPU: <200ps
鈥?/div>
PCI - PCI: <500ps
鈥?/div>
CPU (early - PCI: min=1.0ns, max=2.6ns
鈥?/div>
CPU cycle to cycle jitter: <250ps
Pin Configuration
VDDREF
GND
X1
X2
AVDD48
*FS2/48MHz
*FS3/24_48MHz
GND
PCICLK_F
*SEL24_48#/PCICLK0
PCICLK1
GND
PCICLK2
PCICLK3
VDDPCI
PCICLK4
PCICLK5
PCICLK6
GND
PCICLK7
PCILCK8
PCICLK9_E
VDDPCI
SRESET#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0/FS0*
REF1/FS1*
REF_F
REF_STOP#*
AGP_STOP#*
GND
CPUCLKT0
CPUCLKC0
VDDL
CPUCLK_CST0
CPUCLK_CSC0
GND
CPU_STOP#*
PCI_STOP#*
PD#*
AVDD
AGND
SDATA
SCLK
GND
AGP2
AGP1
AGP0
VDDAGP
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
2
Functionality
48MHz (1:0)
24_48MHz
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
REF (1:0)
REF_F
CPU
DIVDER
Stop
CPUCLKT0
CPUCLKC0
CPUCLK_CST0
CPUCLK_CSC0
PCICLK9_E
CPU
DIVDER
Stop
SEL24_48#
SDATA
SCLK
FS (3:0)
PD#
PCI_STOP#
CPU_STOP#
AGP_STOP#
REF_STOP#
0447E鈥?5/07/04
Control
Logic
PCI
DIVDER
Stop
9
PCICLK (8:0)
PCICLK_F
AGP
DIVDER
Stop
3
AGP (2:0)
Config.
Reg.
SRESET#
CPU
(MHz)
233.33
220.00
210.00
200.00
190.00
180.00
170.00
150.00
140.00
120.00
110.00
66.67
200.00
166.67
100.00
133.33
ICS94228
AG P
(MHz)
77.78
73.33
70.00
66.67
76.00
72.00
68.00
75.00
70.00
60.00
66.00
66.67
66.67
66.67
66.67
66.67
PCICLK
(MHz)
38.88
36.67
35.00
33.33
38.00
36.00
34.00
37.50
35.00
30.00
33.00
33.33
33.33
33.33
33.33
33.33

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