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ICS94206YF-T Datasheet

  • ICS94206YF-T

  • Programmable System Frequency Generator for PII/III⑩

  • 18頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS94206
Programmable System Frequency Generator for PII/III鈩?/div>
Recommended Application:
440BX - VIA Apollo Pro133 - ALI 1631 style chipset.
Output Features:
鈥?/div>
2 - CPUs @2.5V
鈥?/div>
1 - IOAPIC @ 2.5V
鈥?/div>
13 - SDRAM @ 3.3V
鈥?/div>
6 - PCI @3.3V,
鈥?/div>
1 - 48MHz, @3.3V
鈥?/div>
1 - 24MHz @ 3.3V
鈥?/div>
2 - REF @3.3V, 14.318MHz.
Features:
鈥?/div>
Programmable ouput frequency.
鈥?/div>
Programmable ouput rise/fall time.
鈥?/div>
Programmable PCI_F and PCICLK skew.
鈥?/div>
Spread spectrum for EMI control typically by 7dB to
8dB,
with programmable spread percentage.
鈥?/div>
Watchdog timer technology to reset system
if over-clocking causes malfunction.
鈥?/div>
Uses external 14.318MHz crystal.
鈥?/div>
FS pins for frequency select
Key Specifications:
鈥?/div>
CPU 鈥?CPU: <175ps
鈥?/div>
SDRAM - SDRAM: <500ps
鈥?/div>
PCI 鈥?PCI: <500ps
鈥?/div>
CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Pin Configuration
VDD1
*PCI_STOP/REF0
GND
X1
X2
VDD2
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDD2
BUFFER IN
GND
SDRAM11
SDRAM10
VDD3
SDRAM9
SDRAM8
GND
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDL1
IOAPIC
REF1/FS2*
GND
CPUCLK_F
CPUCLK1
VDDL2
CLK_STOP#*
SDRAM_F
GND
SDRAM0
SDRAM1
VDD3
SDRAM2
SDRAM3
GND
SDRAM4
SDRAM5
VDD3
SDRAM6
SDRAM7
VDD4
48MHz/FS0*
24MHz/FS1*
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
Functionality
Block Diagram
PLL2
/2
X1
X2
BUFFER IN
XTAL
OSC
48MHz
24MHz
IOAPIC
REF(1:0)
CPUCLK_F
PLL1
Spread
Spectrum
FS(3:0)
4
MODE
STOP
ICS94206
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
STOP
2
CPUCLK 1
LATCH
STOP
12
SDRAM (11:0)
SDRAM_F
4
POR
CLK_STOP#
PCI_STOP#
SDATA
SCLK
Control
Logic
Config.
Reg.
PCI
CLOCK
DIVDER
STOP
5
PCICLK (4:0)
PCICLKF
CPU
(MHz)
80.00
75.00
83.31
66.82
103.00
112.01
68.01
100.23
120.00
114.99
109.99
105.00
140.00
150.00
124.00
132.99
PCICLK
(MHz)
40.00
37.50
41.65
33.41
34.33
37.34
34.01
33.41
40.00
38.33
36.66
35.00
35.00
37.50
31.00
33.25
94206 Rev B 04/26/01
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

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