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Integrated

Circuit

Systems, Inc.

ICS93V857-XXX

2.5V Wide Range Frequency Clock Driver (33MHz - 233MHz)

Recommended Application:

鈥?DDR Memory Modules / Zero Delay Board Fan Out

鈥?Provides complete DDR DIMM logic solution with

ICSSSTV16857, ICSSSTV16859 or ICSSSTV32852

Product Description/Features:

鈥?Low skew, low jitter PLL clock driver

鈥?1 to 10 differential clock distribution (SSTL_2)

鈥?Feedback pins for input to output synchronization

鈥?PD# for power management

鈥?Spread Spectrum tolerant inputs

鈥?Auto PD when input signal removed

鈥?Choice of static phase offset available,

for easy board tuning;

-XXX = device pattern number for options listed

below.

-

ICS93V857-025 ......

0ps

-

ICS93V857-125

+125ps

-

ICS93V857-130 ..

+40ps

Switching Characteristics:

鈥?Period jitter (>66MHz): <40ps

鈥?CYCLE - CYCLE jitter (66MHz): <120ps

鈥?CYCLE - CYCLE jitter (>100MHz): <65ps

鈥?OUTPUT - OUTPUT skew: <60ps

鈥?Output Rise and Fall Time: 650ps - 950ps

鈥?DUTY CYCLE: 49.5% - 50.5%

Pin Configuration

GND

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

GND

CLKC2

CLKT2

VDD

VDD

CLK_INT

CLK_INC

VDD

AVDD

AGND

GND

CLKC3

CLKT3

VDD

CLKT4

CLKC4

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

GND

CLKC5

CLKT5

VDD

CLKT6

CLKC6

GND

GND

CLKC7

CLKT7

VDD

PD#

FB_INT

FB_INC

VDD

FB_OUTC

FB_OUTT

GND

CLKC8

CLKT8

VDD

CLKT9

CLKC9

GND

48-Pin TSSOP & TVSOP

6.10 mm. Body, 0.50 mm. pitch = TSSOP

4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)

Block Diagram

FB_OUTT

FB_OUTC

CLKT0

CLKC0

ICS93V857-025/125/130

Functionality

Control

CLKT1

CLKC1

INPUTS

AVDD PD#

GND

GND

2.5V

(nom)

2.5V

(nom)

2.5V

(nom)

2.5V

(nom)

2.5V

(nom)

H

H

L

L

H

H

X

CLK_INT

L

H

L

H

L

H

<20MHz)

(1)

OUTPUTS

PLL State

CLK_INC CLKT CLKC FB_OUTT FB_OUTC

H

L

H

L

H

L

L

H

Z

Z

L

H

Z

H

L

Z

Z

H

L

Z

L

H

Z

Z

L

H

Z

H

L

Z

Z

H

L

Z

Bypassed/off

Bypassed/off

off

off

on

on

off

PD#

Logic

CLKT2

CLKC2

CLKT3

CLKC3

CLKT4

CLKC4

FB_INT

FB_INC

CLK_INC

CLK_INT

CLKT5

CLKC5

PLL

CLKT6

CLKC6

CLKT7

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

0693K鈥?3/13/03

1

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