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Integrated

Circuit

Systems, Inc.

ICS93V850

Preliminary Product Preview

DDR Phase Lock Loop Clock Driver

Recommended Application:

DDR Clock Driver

Product Description/Features:

鈥?Low skew, low jitter PLL clock driver

鈥?I

2

C for functional and output control

鈥?Feedback pins for input to output synchronization

鈥?Spread Spectrum tolerant inputs

鈥?With bypass mode mux

鈥?Operating frequency 60 to 140 MHz

Switching Characteristics:

鈥?PEAK - PEAK jitter (66MHz): <120ps

鈥?PEAK - PEAK jitter (>100MHz): <75ps

鈥?CYCLE - CYCLE jitter (66MHz):<120ps

鈥?CYCLE - CYCLE jitter (>100MHz):<65ps

鈥?OUTPUT - OUTPUT skew: <100ps

鈥?Slew Rate: 1V/ns - 2V/ns

GND

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

GND

CLKC2

CLKT2

VDD

SCLK

CLK_INT

CLK_INC

2

VDDI C

AVDD

AGND

GND

CLKC3

CLKT3

VDD

CLKT4

CLKC4

GND

Pin Configuration

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

GND

CLKC5

CLKT5

VDD

CLKT6

CLKC6

GND

GND

CLKC7

CLKT7

VDD

SDATA

FB_INC

FB_INT

VDD

FB_OUTT

FB_OUTC

GND

CLKC8

CLKT8

VDD

CLKT9

CLKC9

GND

48-Pin TSSOP

Block Diagram

FB_OUTT

FB_OUTC

CLKT0

CLKC0

CLKT1

CLKC1

Functionality

INPUTS

GND

GND

L

H

H

L

H

L

<20 MHz

L

H

L

H

Hi-Z

H

L

H

L

Hi-Z

OUTPUTS

L

H

L

H

Hi-Z

H

L

H

L

Hi-Z

AVDD CLK_INT CLK_INC CLKT CLKC FB_OUTT FB_OUTC

PLL State

Bypassed/Off

Bypassed/Off

On

On

Off

SCLK

SDATA

Control

Logic

CLKT2

CLKC2

CLKT3

CLKC3

CLKT4

CLKC4

2.5V

L

(nom)

2.5V

H

(nom)

2.5V

<20 MHz

(nom)

FB_INT

FB_INC

CLK_INC

CLK_INT

CLKT5

CLKC5

PLL

CLKT6

CLKC6

CLKT7

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

AVDD

0423H鈥?7/03/03

PRODUCT PREVIEW

documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to

change without notice.

ICS93V850

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