Integrated
Circuit
Systems, Inc.
ICS93735
DDR Phase Lock Loop Zero Delay Clock Buffer
Recommended Application:
DDR Zero Delay Clock Buffer
Product Description/Features:
鈥?Low skew, low jitter PLL clock driver
鈥?Max frequency supported = 266MHz (DDR 533)
鈥?I
2
C for functional and output control
鈥?Feedback pins for input to output synchronization
鈥?Spread Spectrum tolerant inputs
鈥?3.3V tolerant CLK_INT input
Switching Characteristics:
鈥?CYCLE - CYCLE jitter (66MHz): <120ps
鈥?CYCLE - CYCLE jitter (>100MHz): <65ps
鈥?CYCLE - CYCLE jitter (>200MHz): <75ps
鈥?OUTPUT - OUTPUT skew: <100ps
鈥?Output Rise and Fall Time: 500ps - 700ps
鈥?DUTY CYCLE: 49.5% - 50.5%
Pin Configuration
Functionality
OUTPUTS
AVDD
CLK_INT
CLKT
CLKC
FB_OUTT
2.5V (nom)
L
L
H
L
2.5V (nom)
H
H
L
H
2.5V (nom)
< offset freq* offset freq* offset freq* offset freq*
GND
L
L
H
L
GND
H
H
L
H
* The offset frequency is ~ 20 MHz, varying somewhat from part to part.
INPUTS
PLL State
on
on
off
Bypassed/off
Bypassed/off
48-Pin SSOP
Block Diagram
FB_OUTT
CLKT0
CLKC0
CLKT1
CLKC1
SCLK
SDATA
Control
Logic
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
FB_INT
CLK_INT
PLL
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
0579E鈥?8/06/03