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Integrated

Circuit

Systems, Inc.

ICS93725

DDR and SDRAM Zero Delay Buffer

Recommended Application:

DDR & SDRAM Zero Delay Buffer for SIS 635/640/645/

650 & 735/740/746 style chipsets.

Product Description/Features:

鈥?Low skew, Zero Delay Buffer

鈥?1 to 13 SDRAM PC133 clock distribution

鈥?1 to 6 pairs of DDR clock distribution

鈥?I

2

C for functional and output control

鈥?Separate feedback path for both memory mode to

adjust synchronization.

鈥?Supports up to 2 DDR DIMMs or 3 SDRAM DIMMs

鈥?Frequency support for up to 200MHz

鈥?Individual I

2

C clock stop for power mananagement

鈥?CMOS level control signal input

Switching Characteristics:

鈥?OUTPUT - OUTPUT skew: <100ps

鈥?Output Rise and Fall Time for DDR outputs: 550ps -

1150ps

鈥?DUTY CYCLE: 47% - 53%

Pin Configuration

VDD3.3

SDRAM0

SDRAM1

SDRAM2

SDRAM3

GND

VDD3.3

SDRAM4

SDRAM5

BUFFER_IN

SDRAM6

SDRAM7

GND

VDD3.3

SDRAM8

SDRAM9

SDRAM10

SDRAM11

GND

VDD3.3

SDRAM12

SDFB_OUT

SDFB_IN

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

SEL_DDR*

DDRFB_IN

DDRFB_OUT

VDD2.5

DDRT5

DDRC5

DDRT4

DDRC4

GND

VDD2.5

DDRT3

DDRC3

DDRT2

DDRC2

GND

VDD2.5

DDRT1

DDRC1

DDRT0

DDRC0

GND

VDD2.5

SCLK

SDATA

48-Pin SSOP

*Internal Pull-up Resistor of 120K to VDD

Block Diagram

SDRAMFB_OUT

PLL1

DDRFB_OUT

SDRAM (12:0)

Control

SEL_DDR*

SDATA

SCLK

Config.

Reg.

Logic

3

3

Functionality

MODE

PIN 48

SEL_DDR=1

SEL_DDR=0

VDD

3.3_2.5

2.5V

3.3V

BUFFER_IN

SDRAMFB_IN

DDRFB_IN

DDR

Mode

DDR/SD

Mode

DDRT (5:0)

DDRCC (5:0)

0606A鈥?8/01/03

ICS93725

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