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Integrated

Circuit

Systems, Inc.

ICS93705

DDR Phase Lock Loop Zero Delay Clock Buffer

Recommended Application:

DDR Zero Delay Clock Buffer

Product Description/Features:

鈥?Low skew, low jitter PLL clock driver

鈥?I

2

C for functional and output control

鈥?Feedback pins for input to output synchronization

鈥?Spread Spectrum tolerant inputs

鈥?3.3V tolerant CLK_INT input

Switching Characteristics:

鈥?PEAK - PEAK jitter (66MHz): <120ps

鈥?PEAK - PEAK jitter (>100MHz): <75ps

鈥?CYCLE - CYCLE jitter (66MHz):<120ps

鈥?CYCLE - CYCLE jitter (>100MHz):<65ps

鈥?OUTPUT - OUTPUT skew: <100ps

鈥?Output Rise and Fall Time: 450ps - 950ps

鈥?DUTY CYCLE: 49% - 51%

GND

CLKC0

CLKT0

VDD

CLKT1

CLKC1

GND

GND

CLKC2

CLKT2

VDD

SCLK

CLK_INT

N/C

VDD

AVDD

AGND

GND

CLKC3

CLKT3

VDD

CLKT4

CLKC4

GND

Pin Configuration

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

GND

CLKC5

CLKT5

VDD

CLKT6

CLKC6

GND

GND

CLKC7

CLKT7

VDD

SDATA

N/C

FB_INT

VDD

FB_OUTT

N/C

GND

CLKC8

CLKT8

VDD

CLKT9

CLKC9

GND

48-Pin SSOP

Block Diagram

FB_OUTT

CLKT0

CLKC0

CLKT1

CLKC1

Functionality

INPUTS

AVDD CLK_INT

2.5V

(nom)

2.5V

(nom)

L

H

OUTPUTS

CLKT CLKC FB_OUTT

L

H

Z

L

H

H

L

Z

H

L

L

H

Z

L

H

PLL State

on

on

off

Bypassed/off

Bypassed/off

SCLK

SDATA

Control

Logic

CLKT2

CLKC2

CLKT3

CLKC3

CLKT4

CLKC4

CLKT5

CLKC5

2.5V

<20MHz

(1)

(nom)

GND

GND

L

H

FB_INT

CLK_INT

PLL

CLKT6

CLKC6

CLKT7

CLKC7

CLKT8

CLKC8

CLKT9

CLKC9

0418C鈥?8/08/02

ICS93705

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