鈥?/div>
MREF Output jitter <250ps
Pin Configuration
GND
MULTSEL0/REF
MULTSEL1/REF
VDDREF
X1
X2
GNDREF
PCICLK0
PCICLK1
VDDPCI
PCICLK2
PCICLK3
GNDPCI
PCICLK4
PCICLK5
VDDPCI
PCICLK6
PCICLK7
GNDPCI
PCICLK8
PCICLK9
VDDPCI
SEL100/133
GND48
FS0/48MHz
FS1/48MHz
VDD48
PD#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDMREF
3VMREF
3VMREF_B
GNDMREF
SPREAD#
CPUCLKST3
CPUCLKSC3
VDDCPU
CPUCLKST2
CPUCLKSC2
GNDCPU
CPUCLKST1
CPUCLKSC1
VDDCPU
CPUCLKST0
CPUCLKSC0
GNDCPU
I REF
VDDA
GNDA
VDD3V66
3V66-3
3V66-2
GND3V66
GND3V66
3V66-1
3V66-0
VDD3V66
56-Pin 300mil SSOP & TSSOP
Functionality
SEL133/
100
0
0
0
0
1
1
1
1
FS0
0
0
1
1
0
0
1
1
FS1
0
1
0
1
0
1
0
1
Function
Active 100MHz
(Reserved)
(Reserved)
Tristate all outputs
Active 133MHz
(Reserved)
(Reserved)
Test Mode
3VMREF
DIVDER
Block Diagram
PLL2
2
ICS9250-22
48MHz
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
2
REF
CPU
DIVDER
4
4
CPUCLKST (3:0)
CPUCLKSC (3:0)
3VMREF
3VMREF_B
Power Groups
VDDREF, GNDREF= REF, X1, X2
VDDPCI, GNDPCI = PCICLK
VDD48, GND48 = 48MHz, PLL2
VDD3V66, GND3V66=3V66
VDDCPU, GNDCPU = CPUCLK
VDDMREF, GNDMREF=3VMREF, 3VMREF_B
VDDA=VDD (core supply voltage 3.3V)
GNDA=Ground for core supply
9250-22 Rev B 12/08/00
Third party brands and names are the property of their respective owners.
PD#
SPREAD#
MULTSEL (1:0)
SEL100/133
FS(1:0)
Control
Logic
Config.
Reg.
3V66
DIVDER
4
PCI
DIVDER
10
PCICLK (9:0)
3V66 (3:0)
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.