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ICS9250YF-32-T Datasheet

  • ICS9250YF-32-T

  • Frequency Generator & Integrated Buffers for PII/III⑩

  • 11頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9250-32
Frequency Generator & Integrated Buffers for PII/III鈩?/div>
Recommended Application:
Timna Style Chipset
Output Features:
鈥?/div>
3 - CPUs @ 2.5V
鈥?/div>
8 - PCI @ 3.3V
鈥?/div>
2 - IOAPIC @ 2.5V
鈥?/div>
1 - MREF @ 2.5V, DRCG memory reference clock
鈥?/div>
9 - SDRAM @ 3.3V including one free running
鈥?/div>
1 - 2V48M @ 2.5V fixed (DOT)
鈥?/div>
1 - 3V48M @ 3.3V fixed (USB)
鈥?/div>
2 - REF @ 3.3V, 14.318MHz.
Features:
鈥?/div>
Support power management: CPU, PCI, SDRAM stop
from I
2
C programming.
鈥?/div>
Spread spectrum for EMI control (0 to -0.5%)
鈥?/div>
Uses external 14.318MHz crystal
Key Specifications:
鈥?/div>
CPU Output Jitter
(Cyc-Cyc)
: <175ps
鈥?/div>
IOAPIC Output Jitter
(Cyc-Cyc)
: <500ps
鈥?/div>
MREF Output Jitter
(Cyc-Cyc)
: <250ps
鈥?/div>
2V48M Output Jitter
(Cyc-Cyc)
: <250ps
鈥?/div>
3V48M Output Jitter
(Cyc-Cyc)
: <500ps
鈥?/div>
CPU - CPU: < 175ps
鈥?/div>
SDRAM - SDRAM < 250ps
鈥?/div>
PCI - PCI: < 500ps
鈥?/div>
IOAPIC - IOAPIC: < 250ps
鈥?/div>
BUFFER_IN to SDRAM prop delay: 5.5 to 7.5ns
Pin Configuration
2V48M
3V48M
VDD48
GND48
X1
X2
GND
*(CPU2_EN#)REF0
REF1
VDD
PCICLK0
PCICLK1
GNDPCI
VDDPCI
PCICLK2
PCICLK3
PCICLK4
PCICLK5
VDDPCI
GNDPCI
PCICLK6
PCICLK7
SCLK
VDDA
GNDA
SDATA
BUF_IN
*FS0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDLIOAPIC
IOAPIC0
IOAPIC1
GNDLIOAPIC
VDDLCPU
CPUCLK0
CPUCLK1
VDDLCPU
GNDLCPU
CPUCLK2
MREF66
VDD
SDRAM_F
SDRAM0
VDDSDR
GNDSDR
SDRAM1
SDRAM2
SDRAM3
GNDSDR
VDDSDR
SDRAM4
SDRAM5
VDDSDR
GNDSDR
SDRAM6
SDRAM7
FS1*
56-Pin 300mil SSOP
* These inputs have a 50K pull up to VDD.
Functionality
FS1
Power up Latched
FS0
REF1/CPU2_EN#
1
1
0
1
0
1
0
X
X
X
CPU0
CPU1,
MREF
66MHz
66MHz
TCLK/2
Reserved
Tristate
CPU2
Tristate
66MHz
TCLK/2
Reserved
Tristate
Block Diagram
PLL2
3V48M
2V48M
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
BUF_IN
CPU_EN#
SDATA
SCLK
FS (1:0)
Control
Logic
Config.
Reg.
PCI
DIVDER
8
1
1
2
REF (1:0)
1
CPU
DIVDER
3
CPUCLK (2:0)
0
0
SDRAM
DIVDER
8
SDRAM (7:0)
SDRAM_F
IOAPIC
DIVDER
2
IOAPIC (1:0)
Power Groups
VDD = REF, X1, X2
VDDPCI = PCICLK
VDDSDR = SDRAM
VDD48 = 3V48M
VDDLCPU = CPU
VDDLIOAPIC = IOAPIC, 2V48M
VDDA = PLL Core
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
PCICLK (7:0)
3V66
DIVDER
MREF66
9250-32 Rev B 9/7/00
Third party brands and names are the property of their respective owners.
ICS9250-32

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