鈥?/div>
Alternate frequency selections available through I
2
C
control.
IOAPIC
VDDL
GNDL
*FS1/REF
VDDR
X1
X2
GNDR
VDD3
3V66-0
3V66-1
3V66-2
GND3
PCICLK0
PCICLK1
PCICLK2
VDD2
GND2
PCICLK3
PCICLK4
FS0
GNDA
VDDA
SCLK
SDATA
GNDF
VDDF
48MHz_0
Pin Configuration
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GNDL
VDDL
CPUCLK0
CPUCLK1
GND1
SDRAM0
SDRAM1
VDD1
GND1
SDRAM2
SDRAM3
SDRAM4
SDRAM5
VDD1
GND1
SDRAM6
SDRAM7
SDRAM8
SDRAM9
VDD1
GND1
SDRAM10
SDRAM11
VDD1
GND1
SDRAM12
TRISTATE#/PD#**
48MHz_1
56-Pin 300mil SSOP
* This input has a 50K pull-down to GND.
** This input has a 50K pull-up to VDD
9
9
Block Diagram
Functionality
Tristate#
FS0
0
1
0
1
0
1
FS1
X
X
0
0
1
1
CPU
MHz
Tristate
Test
66MHz
100MHz
133MHz
133MHz
SDRAM
MHz
Tristate
Test
100MHz
100MHz
133MHz
100MHz
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
/2
/3
REF
VDDL
2
CPU66/100/133 [1:0]
3V66 [2:0]
SDRAM [12:0]
PCICLK [4:0]
IOAPIC
VDDL
0
0
1
1
1
1
FS(1:0)
PD#
TRISTATE#
SDATA
SCLK
Control
Logic
Config
Reg
/2
/2
3
13
5
Power Groups
VDDA, GNDA = CPU, PLL (analog)
VDDF, GNDF = Fixed PLL, 48M (analog/digital)
VDDR, GNDR = REF, X1, X2 (analog/digital)
VDD3, GND3 = 3V66 (digital)
VDD2, GND2 = PCI (digital)
VDD1, GND1 = SDRAM (digital)
VDDL, GNDL = IOAPIC, CPU (digital)
PLL2
2
48MHz [1:0]
9250-29 Rev A 02/01/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the
latest version of all device data to verify that any information being relied
upon by the customer is current and accurate.
ICS9250-29