鈥?/div>
Alternate frequency selections available through I
2
C
control.
Pin Configuration
IOAPIC
VDDL
GND
*FS1/REF0
VDDREF
X1
X2
GND
VDD3V66
3V66_0
3V66_1
3V66_2
GND
VDDPCI
PCICLK0
PCICLK1
GND
FS0
GND
VDDA
PD#
SCLK
SDATA
GND
VDD48
48MHz_0
48MHz_1
FS2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDL
GND
CPUCLK0
CPUCLK1
GND
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
SDRAM4
VDDSDR
GND
SDRAM5
SDRAM6
VDDSDR
GND
SDRAM7
SDRAM8
SDRAM9
VDDSDR
GND
SDRAM10
SDRAM11
VDDSDR
GND
SDRAM12
56-Pin 300mil SSOP
* This input has a 50KW pull-down to GND.
Functionality
Block Diagram
FS2
0
0
REF0
PLL1
Spread
Spectrum
/2
/3
2
FS0
0
1
0
1
0
1
FS1
X
X
0
0
1
1
ICS9250-28
Function
Tristate
Test
Active CPU = 66MHz
SDRAM = 100MHz
Active CPU = 100MHz
SDRAM = 100MHz
Active CPU = 133MHz
SDRAM = 133MHz
Active CPU = 133MHz
SDRAM = 100MHz
X1
X2
XTAL
OSC
1
1
CPU66/100/133 [1:0]
3V66 (2:0)
SDRAM (12:0)
PCICLK (1:0)
IOAPIC
1
1
FS(2:0)
PD#
Control
Logic
Config
Reg
/2
/2
3
13
2
SDATA
SCLK
PLL2
Power Groups
Analog
VDDREF = X1, X2
VDDA = PLL1
VDD48 = PLL2
Digital
VDD3V66, VDDPCI
VDDSDR, VDDL
2
48MHz (1:0)
9250-28 Rev B 10/26/00
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.