鈥?/div>
For group skew specification, please refer to group
timing relationships table.
Pin Configuration
48-Pin 300mil SSOP
*: These inputs have a 120K pull up to VDD.
1: These are double strength.
Block Diagram
PLL2
2
Functionality
48MHz
/2
24_48MHz
FS3 FS2 FS1 FS0
CPU
(MHz)
CPU/ SDRAM 3V66
SDRAM (MHz) (MHz)
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
P C I C L K I OA P I C
I OA P I C
(PCI*
(3V66*
(PCI)
1/2)
1/2)
(MHz)
(MHz)
(MHz)
REF1
CPU
DIVDER
2
CPUCLK [1:0]
SDRAM
DIVDER
8
SDRAM [7:0]
SDRAM_F
SEL24_48#
I C
2
{
SDATA
SCLK
FS[3:0]
PD#
Control
Logic
IOAPIC
DIVDER
IOAPIC
Config.
Reg.
PCI
DIVDER
8
PCICLK [7:0]
3V66
DIVDER
3V66 [1:0]
2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
83.3
124.00
155.00
143.96
70.00
112.00
150.00
140.00
68.33
107.00
138.00
137.33
66.80
100.30
133.60
133.60
1.00
1.00
1.00
1.33
0.67
1.00
1.00
1.33
0.67
1.00
1.00
1.33
0.67
1.00
1.00
1.33
83.3 55.48
124.00 82.67
155.00 103.33
108.00 72.00
105.00 70.00
112.00 74.67
150.00 100.00
105.00 70.00
102.50 68.33
107.00 71.33
138.00 92.00
103.00 68.67
100.20 66.80
100.30 66.80
133.60 89.07
100.20 66.80
27.74
41.33
51.67
36.00
35.00
37.33
50.00
35.00
34.17
35.67
46.00
34.34
33.40
33.40
44.53
33.40
13.87
20.67
25.83
18.00
17.50
18.67
25.00
17.50
17.08
17.83
23.00
17.17
16.70
16.70
22.27
16.70
27.74
41.33
51.67
36.00
35.00
37.33
50.00
35.00
34.17
35.67
46.00
34.34
33.40
33.40
44.53
33.40
9248-87 Rev D 10/27/00
Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.