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ICS9248YF-72 Datasheet

  • ICS9248YF-72

  • Frequency Timing Generator for PENTIUM II Systems

  • 12頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9248-72
Preliminary Product Preview
Frequency Timing Generator for PENTIUM II Systems
General Description
The
ICS9248-72
is a main clock synthesizer chip for Pentium
II based systems using Rambus Interface DRAMs. This chip
provides all the clocks required for such a system when used
with a Direct Rambus Clock Generator(DRCG) chip such as
the ICS9211-01.
Spread Spectrum may be enabled by driving the SPREAD#
pin active. Spread spectrum typically reduces system EMI by
8dB to 10dB. This simplifies EMI qualification without resorting
to board design iterations or costly shielding. The
ICS9248-
72
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
The CPU/2 clocks are inputs to the DRCG.
Features
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Up to 200MHz frequency support.
Power Down feature.
Spread Spectrum for EMI control
(0 to 聳0.5% down spread , + 0.25% center spread)
I
2
C interface.
VDDL=2.5V,VDD=3.3V
CPU Output Jitter: <250ps
CPU/2 Output Jitter. <250ps
IOAPIC Output Jitter: <500ps
48MHz, 3V66, PCI Output Jitter: <500ps
Ref Output Jitter. <1000ps
CPU Output Skew: <175ps
IOAPIC Output Skew <250ps
PCI Output Skew: <500ps
3V66 Output Skew <250ps
CPU to 3V66 Output Offset: 0.0 - 1.5ns (CPU leads)
3V66 to PCI Output Offset: 1.5 - 4.0ns (3V66 leads)
CPU to IOAPIC Output Offset 1.5 - 4.0ns (CPU leads)
Key Specification
Block Diagram
Pin Configuration
48-pin SSOP
* 250K ohm pull-up to VDD on indicated inputs.
1.These pins will have 2X drive strength
9248-72 Rev B 7/28/99
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.

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