鈥?/div>
6 PCI (3.3V) @ 33.3MHz (all are free running
selectable).
1 REF (3.3V) at 14.318MHz.
1 48MHz (3.3V).
1 24_48MHz selectable output.
Pin Configuration
GNDREF
X1
X2
PD#
PCICLK0
PCICLK1
PCICLK2
GNDPCI
VDDPCI
PCICLK3
PCICLK4
PCICLK5
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Features:
鈥?Supports Spread Spectrum modulation for CPU and
PCI clocks, default -0.4 downspread.
鈥?Efficient Power management scheme through stop
clocks and power down modes.
鈥?Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
鈥?28-pin TSSOP package, 4.40mm (173mil).
Skew Characteristics:
鈥?CPU 鈥?CPU <175ps
鈥?PCI 鈥?PCI < 500ps
鈥?CPU(early) 鈥?PCI = 1.5ns 鈥?4ns.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDREF
REF
CPU_STOP#
VDDLCPU
GNDLCPU
CPUCLK0
PCI_STOP#
GND_Core
VDD_Core
SEL66/60#
VDD48
GND48
48MHz/CPU3.3v_2.5V#sel
24-48MHz/Sel48_24#
28-Pin TSSOP
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
REF
CPU
DIVDER
Stop
CPUCLK0
SEL48_24#
CPU3.3V_2.5V#sel
SEL66/60#
PD#
PCI_STOP#
CPU_STOP#
SDATA
SCLK
Control
Logic
Config.
Reg.
PCI
DIVDER
Stop
6
PCICLK (5:0)
Power Groups
VDD_Core, GND_Core = PLL core
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (5:0)
VDD48, GND48 = 48MHz (1:0)
0540E鈥?8/20/03
ICS9248-192