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ICS9248YF-189-T Datasheet

  • ICS9248YF-189-T

  • AMD - K7⑩ Clock Generator for Mobile System

  • 15頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9248-189
Advance Information
AMD - K7鈩?Clock Generator for Mobile System
Recommended Application:
VIA K7/KN/KX-133 style chipset
Output Features:
鈥?/div>
1 - Differential pair open drain CPU clocks
鈥?/div>
1 - CPU clock @ 3.3V
鈥?/div>
7 - SDRAM @ 3.3V
鈥?/div>
8 - PCI @ 3.3V,
鈥?/div>
1 - 48MHz, @ 3.3V fixed
鈥?/div>
1 - 24/48MHz @ 3.3V
鈥?/div>
3 - REF @ 3.3V, 14.318MHz.
Features:
鈥?/div>
Up to 166MHz frequency support
鈥?/div>
Support power management via hardware select CPU
stop, CLOCK stop, PCI stop, and SDRAM stop
鈥?/div>
Support power management via I
2
C programing
鈥?/div>
Spread spectrum for EMI control
(鹵 0.25% to 鹵 0.06% center, or 0 to -0.5% or -1.0% down
spread)
鈥?/div>
Uses external 14.318MHz crystal
Key Specifications:
鈥?/div>
CPU - CPU Skew: <175ps
鈥?/div>
CPU - SDRAM Skew: 鹵125ps
鈥?/div>
CPU - PCI Skew: 鹵100ps
鈥?/div>
PCI - PCI Skew: <500ps
Pin Configuration
VDDREF
X1
X2
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK6
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
GND
GND
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0
REF
1
REF2/FS3*
GND
GND
VDD
CPUCLK_CS
2
CPUCLKT0
2
CPUCLKC0
CPU_STOP#*
CLK_STOP#*/PD#
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
1
48-Pin 300mil SSOP & 240mil TSSOP
* Internal Pull-up Resistor of 120K to VDD
1
These outputs have double strength to drive 2 loads.
2
These outputs can be set to 1X or 1.5X strength
through I
2
C
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
3
Functionality
FS2
48MHz
24_48MHz
REF (2:0)
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
CPU
100.00
133.33
100.00
133.33
100.00
133.33
100.00
133.33
ICS9248-189
PCI
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
S p re a d Pe rc e n t a g e
+/- 0.35% Center Spread
+/- 0.35% Center Spread
0 to - 0.5% Down Spread
0 to - 0.5% Down Spread
+/- 0.6% Center Spread
+/- 0.6% Center Spread
No Spread
No Spread
0
0
0
0
1
1
1
1
CPU
DIVDER
Stop
CPUCLK_CS
CPUCLKT0
CPUCLKC0
SEL24_48#
SDATA
SCLK
FS (3:0)
PD#
CPU_STOP#
CLK_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
Control
Logic
PCI
DIVDER
Stop
7
PCICLK (6:0)
PCICLK_F
Note: For a complete functionality table please see table in
page 3.
Power Groups
VDD48 = 48MHz, Fixed PLL
VDDA = VDD for Core PLL
VDDREF = REF, Xtal
Config.
Reg.
SDRAM
DIVIDER
Stop
6
SDRAM (5:0)
SDRAM_F
9248-189 Rev - 08/10/01
Third party brands and names are the property of their respective owners.
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.

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