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ICS9248YF-168-T Datasheet

  • ICS9248YF-168-T

  • AMD - K7⑩ Clock Generator for Mobile System

  • 173.82KB

  • 14頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS9248-168
AMD - K7鈩?Clock Generator for Mobile System
Recommended Application:
VIA KT133 style chipset
Output Features:
鈥?/div>
1 - Differential pair open drain CPU clocks
鈥?/div>
1 - CPU clock @ 3.3V
鈥?/div>
7 - SDRAM @ 3.3V
鈥?/div>
8 - PCI @ 3.3V,
鈥?/div>
1 - 48MHz, @ 3.3V fixed.
鈥?/div>
1 - 24/48MHz @ 3.3V
鈥?/div>
3 - REF @ 3.3V, 14.318MHz.
Features:
鈥?/div>
Up to 153MHz frequency support
鈥?/div>
Support power management: CPU stop and Power down
Mode from I
2
C programming.
鈥?/div>
Spread spectrum for EMI control
(鹵 0.25% to 鹵 0.6% center, or 0 to -0.5% or -1.0% down
spread).
鈥?/div>
Uses external 14.318MHz crystal
Pin Configuration
VDDREF
X1
X2
*FS2/PCICLK_F
*FS1/PCICLK0
VDDPCI
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GND
VDDPCI
PCICLK6
*SDRAM_STOP#
*PCI_STOP#
BUFFER_IN
AVDD
GND
GND
*FS0/48MHZ
*SEL24_48#/24_48MHz
VDD48
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF0
REF
1
REF2
GND
GND
VDD
2
CPUCLK
2
CPUCLKT0
2
CPUCLKC0
CPU_STOP#*
PD#*
SDRAM0
SDRAM1
VDDSDR
GND
SDRAM2
SDRAM3
GND
VDDSDR
SDRAM4
SDRAM5
SDRAM_F
SCLK
SDATA
1
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
1
These outputs have double strength to drive 2 loads.
2
These outputs can be set to 1.5X strength through I
2
C
Block Diagram
PLL2
/2
X1
X2
XTAL
OSC
PLL1
Spread
Spectrum
48MHz
24_48MHz
REF (2:0)
CPUCLK
CPU
DIVDER
Stop
Functionality
FS2
0
0
0
0
1
1
1
CPUCLKT0
FS1
0
0
1
1
0
0
1
1
FS0
0
1
0
1
0
1
0
1
CPU
100.00
133.33
100.00
133.33
100.00
133.33
90.00
120.00
PCI
33.33
33.33
33.33
33.33
33.33
33.33
30.00
30.00
ICS9248-168
S p re a d Pe rc e n t a g e
+/- 0.35% Center Spread
+/- 0.35% Center Spread
0 to - 0.5% Down Spread
0 to - 0.5% Down Spread
+/- 0.6% Center Spread
+/- 0.6% Center Spread
+/- 0.25% Center Spread
+/- 0.25% Center Spread
CPUCLKC0
1
SEL24_48#
SDATA
SCLK
FS (2:0)
PD#
CPU_STOP#
PCI_STOP#
SDRAM_STOP#
BUFFER_IN
Control
Logic
PCI
DIVDER
Stop
PCICLK (6:0)
PCICLK_F
SDRAM
DRIVER
Stop
SDRAM (5:0)
SDRAM_F
Config.
Reg.
9248-168 Rev B 01/09/01
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.

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