鈥?/div>
Compatible with all Direct Rambus
TM
based ICs
Provides differential clock source for direct
Rambus memory system with 1GHz data transfer
rate capability
Cycle to Cycle jitter is less than 100ps
3.3V + 4% supply
LVCMOS REF clock @ crystal frequency
Output edge rate control to minimize EMI
Block Diagram
FS0
X1
X2
Pin Configuration
VDDT
GND
X2
X1
VDD
REF
GND
FS1*
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS0*
VDD
GND
BUSCLKT
BUSCLKC
GND
VDD
FS2*
PLL
REF
VDDT
FS1
FS2
Control
Logic
16-Pin 173 mil TSSOP
* Pins have 60K internal pull-up to VDD
Table 1. PLL Multiplier Selection and Output Frequency
FS0
0
1
Mult
16
21.33
2
BUSCLK
1
400.00
533.30
Notes:
1 Output frequencies are based on 25MHz XTAL Input
multipliers are also applicable to spread spectrum modulated input clocks.
2 Default muliplier value at power up.
0931B鈥?0/25/04
ICS9219
Xtal
OSC
BUSCLKT
BUSCLKC