Integrated
Circuit
Systems, Inc.
ICS9179-06
Zero Delay Buffers
General Description
The
ICS9179-06
generates low skew clock buffers required
for high speed RISC or CISC microprocessor systems such as
Intel PentiumPro. An output enable is provided for testability.
The device is a buffer with low output to output skew. This is
a zero delay buffer device, using an internal PLL. This buffer
can be used for phase synchronization to a master clock. With
the wide PLL loop BW, this buffer is compatible to Spread
Spectrum input clocks from clock generator products such as
the ICS9148-27.
The individual clock outputs are addressable through I
2
C to be
enabled, or stopped in a low state for reduced EMI when the
lines are not needed. The device defaults to zero-delay mode,
but can be programmed with I
2
C for selectable delays -2.7,
+2.0, -0.7 ns (nominal target values).
Features
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Zero delay buffer, 16 outputs
Supports up to four SDRAM DIMMS
Wide PLL loop bandwidth makes this part ideal in
Spread Spectrum applications.
Skew Input to FB_IN 鹵250ps default, with selectable
skew -2.7, +2.0, -0.7ns nominal.
Synchronous clocks skew matched to 250 ps window on
output.
33 to 133MHz input or output frequency.
I
2
C Serial Configuration interface to allow individual
clocks to be stopped, or selectable delays.
Multiple VDD, VSS pins for noise reduction
Slew rate 1.5V/ns into 30pF.
VDD = 3.3 鹵5%, 0 to 70擄C
All outputs (0:15) tristate with OE low
(FB_OUT stays running).
48-Pin SSOP package
Block Diagram
Pin Configuration
Functionality
OE#
0
1
OUTPUT
(0:15)
Hi-Z
1 X INPUT
FB_OUT
1 X INPUT
1 X INPUT
PentiumPro is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
9179-06 Rev F 6/22/99
48-Pin SSOP
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.