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Twelve selectable CPU clocks operate up to 83.3MHz
Maximum CPU jitter of 鹵 200ps
Six BUS clocks support sync or async bus operation
鹵250ps skew for all synchronous clock edges
CPU clocks BUS clocks skew 1-4ns (CPU early)
Integrated buffer outputs drive up to 30pF loads
3.0V - 3.7V supply range, CPU(1:12) outputs
2.5V(2.375-2.62V) VDD option
32-pin SOIC/SOJ package
Logic inputs latched at Power-On for frequency
selection saving pins as Input/Output
48 MHz clock for USB support and 24 MHz clock
for FD.
Pin Configuration
Block Diagram
32-Pin SOIC/SOJ
3.3V鹵10%, 0-70
擄
C
Crystal (X1, X2) = 14.31818 MHz
A D D R E SS
SELECT
C PU (1:12)
(M H z)
BU S (1:6)M H z
48M H z
24M H z
R EF
Functionality
VDD Groups:
VDD = X1, X2, REF/BSEL
VDDC1 = CPU1-6
VDDC2 = CPU7-12 & PLL Core
VDDB = BUS1-6
VDDF = 48/24 MHz
Latched Inputs:
L1 = BSEL
L2 = FS0
L3 = FS1
L4 = FS2
9169C-271RevC060297P
FS2 FS1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
FS0
0
1
0
1
0
1
0
1
50
60
66.8
75.9
55
75.9
83.3
68.5
BSEL=1
25
30
33.4
32
27.5
37.5
41.7
34.25
BSEL=0
32
32
32
32
32
32
32
32
48
48
48
48
48
48
48
48
24
24
24
24
24
24
24
24
REF
REF
REF
REF
REF
REF
REF
REF
Pentium is a trademark of Intel Corporation.
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.