鈥?/div>
Four copies of CPU clock
Six SDRAM (3.3 V TTL), usable as AGP clocks
Seven copies of BUS clock (synchronous with CPU
clock/2 or CPU/2.5 for 75 and 83.3 MHz CPU)
CPU clocks to BUS clocks skew 1-4ns (CPU early)
One IOAPIC clock @14.31818 MHz
Two copies of Ref. clock @14.31818 MHz
One each 48/ 24 MHz (3.3 V TTL)
This device is configured into the
Mobile
mode for
power management of Intel 430 TX
Ref. 14.31818 MHz Xtal oscillator input
Separate 66/60 MHz select pin (LSB of select pins)
Separate V
DD2
for four CPU and single IOAPIC output
buffers to allow 2.5V output (or Std. Vdd)
Power Management Control Input pins
3.0V 鈥?3.7V supply range w/2.5V compatible outputs
48-pin SSOP package
Block Diagram
Pin Configuration
48-Pin SSOP
Pentium is a trademark of Intel Corporation
9147-01Rev B 04/25/01
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all
device data to verify that any information being relied upon by the customer is current
and accurate.