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Frequency range 0 - 133 MHz (3.3V)
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 pin 150 mil SOIC &
173 mil TSSOP packages.
3.3V 鹵10% operation
Block Diagram
CLK0
Pin Configuration
CLK0
VDD
GND
1
2
3
4
ICS9112-26
8
7
6
5
CLK_IN
CLK3
VDD
CLK2
CLK1
CLK_IN
CLK2
CLK1
8 pin SOIC & TSSOP
CLK3
Pin Descriptions
PIN NUMBER
1
2,6
3
4
5
7
8
PIN NAME
CLK0
1
VDD
GND
CLK1
1
CLK2
1
CLK3
1
CLK_IN
TYPE
OUT
PWR
PWR
OUT
OUT
OUT
IN
Buffered clock output
Power Supply (3.3V)
Ground
Buffered clock output
Buffered clock output
Buffered clock output
Input reference frequency.
DESCRIPTION
Notes:
1. Weak pull-down on all outputs
9112-26 Rev B- 07/16/01
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.