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ICS87931BYIT Datasheet

  • ICS87931BYIT

  • LOW SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BU...

  • 14頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS87931I
L
OW
S
KEW
, 1-
TO
-6
LVCMOS/LVTTL C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
F
EATURES
鈥?/div>
Fully integrated PLL
鈥?/div>
6 LVCMOS/LVTTL outputs, 7鈩?typical output impedance
鈥?/div>
Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock
for redundant clock applications
鈥?/div>
Maximum output frequency: 150MHz
鈥?/div>
VCO range: 220MHz to 480MHz
鈥?/div>
External feedback for 鈥渮ero delay鈥?clock regeneration
鈥?/div>
Output skew, Same Frequency: 300ps (maximum)
鈥?/div>
Output skew, Different Frequency: 400ps (maximum)
鈥?/div>
Cycle-to-cycle jitter: 100ps (maximum)
鈥?/div>
3.3V supply voltage
鈥?/div>
-40擄C to 85擄C ambient operating temperature
鈥?/div>
Pin compatible with MPC931
G
ENERAL
D
ESCRIPTION
The ICS87931I is a low voltage, low skew
LVCMOS/LVTTL Clock Multiplier/Zero Delay
HiPerClockS鈩?/div>
Buffer and a member of the HiPerClockS鈩?family
of High Performance Clock Solutions from ICS.
With output frequencies up to 150MHz, the
ICS87931I is targeted for high performance clock applications.
Along with a fully integrated PLL, the ICS87931I contains fre-
quency configurable outputs and an external feedback input for
regenerating clocks with 鈥渮ero delay鈥?
,&6
Selectable clock inputs, CLK1 and differential CLK0, nCLK0
support redundant clock applications. The CLK_SEL input de-
termines which reference clock is used. The output divider val-
ues of Bank A, B and C are controlled by the DIV_SELA,
DIV_SELB and DIV_SELC, respectively.
For test and system debug purposes, the PLL_SEL input al-
lows the PLL to be bypassed. When LOW, the nMR input re-
sets the internal dividers and forces the outputs to the high im-
pedance state.
The effective fanout of the ICS87931I can be increased to 12
by utilizing the ability of each output to drive two series termi-
nated transmission lines.
P
IN
A
SSIGNMENT
DIV_SELC
DIV_SELB
DIV_SELA
GND
V
DDO
QA0
QA1
nc
32 31 30 29 28 27 26 25
nc
V
DDA
POWER_DN
CLK1
nMR
CLK0
nCLK0
GND
1
2
3
4
5
6
7
8
24
23
GND
QB0
QB1
V
DDO
EXTFB_SEL
CLK_SEL
PLL_SEL
nc
ICS87931I
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y package
Top View
9 10 11 12 13 14 15 16
nc
CLK_EN0
CLK_EN1
EXT_FB
V
DDO
QC0
QC1
GND
22
21
20
19
18
17
B
LOCK
D
IAGRAM
POWER_DN
Pullup
PLL_SEL
Pullup
CLK_SEL
Pulldown
CLK1
Pullup
CLK0
Pullup
1
0
PHASE
DETECTOR
LPF
1
0
梅8
VCO
0
0
1
梅2
1
QA1
梅2/梅4
QB0
QB1
梅2/梅4
QA0
nCLK0
None
EXTFB_SEL
EXT_FB
Pulldown
Pullup
DIV_SELA
Pulldown
DIV_SELB
Pulldown
CLK_EN0
Pullup
CLK_EN1
Pullup
DIV_SELC
Pulldown
nMR
Pullup
POWER-ON RESET
梅4/梅6
DISABLE
LOGIC
QC0
QC1
87931BYI
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 23, 2003

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