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ICS8752CYT Datasheet

  • ICS8752CYT

  • LOW SKEW, 1-TO-8 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

  • 15頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS8752
L
OW
S
KEW
, 1-
TO
-8
LVCMOS C
LOCK
M
ULTIPLIER
/Z
ERO
D
ELAY
B
UFFER
F
EATURES
鈥?/div>
Fully integrated PLL
鈥?/div>
8 LVCMOS outputs, 7鈩?typical output impedance
鈥?/div>
Selectable LVCMOS CLK0 or CLK1 inputs for
redundant clock applications
鈥?/div>
Input/Output frequency range: 18.33MHz to 240MHz
at V
CC
= 3.3V 鹵 5%
鈥?/div>
VCO range: 220MHz to 480MHz
鈥?/div>
External feedback for 鈥渮ero delay鈥?clock regeneration
鈥?/div>
Cycle-to-cycle jitter: 75ps (maximum),
(all outputs are the same frequency)
鈥?/div>
Output skew: 100ps (maximum)
鈥?/div>
Bank skew: 55ps (maximum)
鈥?/div>
3.3V or 2.5V supply voltage
鈥?/div>
0擄C to 70擄C ambient operating temperature
鈥?/div>
Industrial temperature information available upon request
鈥?/div>
Functionally compatible with MPC952 in some applications
G
ENERAL
D
ESCRIPTION
The ICS8752 is a low voltage, low skew
LVCMOS clock generator and a member of
HiPerClockS鈩?/div>
the HiPerClockS鈩?family of High Performance
Clock Solutions from ICS. With output fre-
quencies up to 240MHz, the ICS8752 is targeted
for high performance clock applications. Along with a fully in-
tegrated PLL, the ICS8752 contains frequency configurable
outputs and an external feedback input for regenerating clocks
with 鈥渮ero delay鈥?
,&6
Dual clock inputs, CLK0 and CLK1, support redundant clock
applications. The CLK_SEL input determines which reference
clock is used. The output divider values of Bank A and B are
controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively.
For test and system debug purposes, the PLL_SEL input
allows the PLL to be bypassed. When HIGH, the MR/nOE
input resets the internal dividers and forces the outputs to
the high impedance state.
The low impedance LVCMOS outputs of the ICS8752 are
designed to drive terminated transmission lines. The effec-
tive fanout of each output can be doubled by utilizing the
ability of each output to drive two series terminated trans-
mission lines.
B
LOCK
D
IAGRAM
PLL_SEL
PLL
FB_IN
CLK0
0
CLK1
1
CLK_SEL
DIV_SELA1
DIV_SELA0
00
01
10
11
PHASE
DETECTOR
VCO
1
0
梅2
梅4
梅6
梅8
梅12
00
01
10
11
P
IN
A
SSIGNMENT
PLL_SEL
GND
GND
V
DDO
QB3
QB2
V
DD
nc
32 31 30 29 28 27 26 25
QA0
QA1
QA2
QA3
DIV_SELB0
DIV_SELB1
DIV_SELA0
DIV_SELA1
MR/nOE
CLK0
QB0
QB1
QB2
QB3
CLK_SEL
V
DDA
V
DD
CLK1
GND
QA0
QA1
V
DDO
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
24
23
22
GND
QB1
QB0
V
DDO
V
DDO
QA3
QA2
GND
ICS8752
21
20
19
18
17
GND
FB_IN
DIV_SELB1
DIV_SELB0
MR/nOE
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
8752CY
www.icst.com/products/hiperclocks.html
1
REV. A AUGUST 19, 2002

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