Divider and a member of the HiPerClockS鈩?/div>
family of High Performance Clock Solutions from
ICS. The ICS8737-11 has two selectable clock
inputs. The CLK, nCLK pair can accept most standard differ-
ential input levels. The PCLK, nPCLK pair can accept
LVPECL, CML, or SSTL input levels.The clock enable is
internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the
clock enable pin.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8737-11 ideal for clock distribution applications
demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
QA0
nQA0
CLK_EN
D
Q
LE
CLK
nCLK
PCLK
nPCLK
CLK_SEL
MR
0
1
梅1
梅2
QB0
nQB0
QB1
nQB1
QA1
nQA1
P
IN
A
SSIGNMENT
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
PCLK
nPCLK
nc
MR
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QA0
nQA0
V
CC
QA1
nQA1
QB0
nQB0
V
CC
QB1
nQB1
ICS8737-11
20-Lead TSSOP
6.50mm x 4.40mm x 0.92 package body
G Package
Top View
8737AG-11
www.icst.com/products/hiperclocks.html
1
REV. A JULY 13, 2001