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ICS87354AMIT Datasheet

  • ICS87354AMIT

  • -2.5V/ 3.3V LVPECL CLOCK GENERATOR

  • 10頁

  • ETC

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PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS87354I
梅4/梅5 D
IFFERENTIAL
-
TO
-2.5V/3.3V
LVPECL C
LOCK
G
ENERATOR
F
EATURES
鈥?1 differential 2.5V/3.3V LVPECL / ECL output
鈥?1 CLK, nCLK input pair
鈥?CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
鈥?Maximum output frequency: 250MHz
鈥?Input frequency: >1GHz
鈥?Translates any single ended input signal to
3.3V LVPECL levels with resistor bias on nCLK input
鈥?Output skew: 38ps (maximum)
鈥?Part-to-part skew: 375ps (maximum)
鈥?Propagation delay: 2.1ns (maximum)
鈥?LVPECL mode operating voltage supply range:
V
CC
= 2.375V to 3.8V, V
EE
= 0V
鈥?ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -2.375V to -3.8V
鈥?-40擄C to 85擄C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS87354I is a high performance 梅4/梅5 Dif-
ferential-to-2.5V/3.3V ECL/LVPECL Clock Genera-
HiPerClockS鈩?/div>
tor and a member of the HiPerClockS鈩?family of
High Performance Clock Solutions from ICS. The
CLK, nCLK pair can accept most standard differ-
ential input levels. The ICS87354I is characterized to operate
from either a 2.5V or a 3.3V power supply. Guaranteed output
and part-to-part skew characteristics make the ICS87354I ideal
for those clock distribution applications demanding well defined
performance and repeatability.
,&6
B
LOCK
D
IAGRAM
CLK
nCLK
R
梅
4
梅
5
0
1
Q
nQ
P
IN
A
SSIGNMENT
CLK
nCLK
MR
F_SEL
1
2
3
4
8
7
6
5
Vcc
Q
nQ
V
EE
MR
ICS87354I
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
F_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
87354AMI
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 27, 2003

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