Integrated
Circuit
Systems, Inc.
ICS8701-01
L
OW
S
KEW
賂1, 賂2
C
LOCK
G
ENERATOR W
/P
OLARITY
C
ONTROL
F
EATURES
聲 20 LVCMOS outputs, 7鈩?typical output impedance
聲 Output frequency up to 250 MHz
聲 250ps bank skew, 300ps output skew, 350ps multiple
frequency skew, 700ps part-to-part skew
聲 Selectable inverting and non-inverting outputs
聲 LVCMOS / LVTTL clock input
聲 LVCMOS / LVTTL control inputs
聲 Bank enable logic allows unused banks to be disabled
in reduced fanout applications
聲 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
聲 48 lead low-profile QFP (LQFP), 7mm x 7mm x 1.4mm
package body, 0.5mm package lead pitch
聲 0擄C to 70擄C ambient operating temperature
聲 Other divide values available on request
The ICS8701-01 is a low skew,
梅1, 梅2
Clock
Generator and a member of the HiPerClockS聶
HiPerClockS鈩?/div>
family of High Performance Clock Solutions
from ICS. The low impedance LVCMOS outputs
are designed to drive 50鈩?series or parallel ter-
minated transmission lines. The effective fanout can be in-
creased from 20 to 40 by utilizing the ability of the outputs to
drive two series terminated lines.
G
ENERAL
D
ESCRIPTION
,&6
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the 梅1,
梅2 or a combination of 梅1 and 梅2 modes. The master reset/
output enable input, nMR/OE, resets the internal dividers and
controls the active and high impedance states of all outputs.
The output polarity inputs, INV0:1, control the polarity (invert-
ing or non-inverting) of the outputs of each bank. Outputs
QA0-QA4 are inverting for every combination of the INV0:1
input. The timing relationship between the inverting and non-
inverting outputs at different frequencies is shown in the Tim-
ing Diagrams.
The ICS8701-01 is characterized at 3.3V and mixed 3.3V in-
put supply, and 2.5V output supply operating modes. Guar-
anteed bank, output and part-to-part skew characteristics
make the ICS8701-01 ideal for those clock distribution appli-
cations demanding well defined performance and repeatabil-
ity.
B
LOCK
D
IAGRAM
梅1
1
0
P
IN
A
SSIGNMENT
GND
QB2
GND
QB3
VDDOB
QB4
QC0
VDDOC
QC1
GND
QC2
GND
LVCMOS_CLK
DIV_SELA
梅2
QAO - QA4
QC3
VDDOC
QC4
QD0
VDDOD
QD1
GND
QD2
GND
QD3
VDDOD
QD4
1
0
QB0 - QB4
DIV_SELB
1
0
QC0 - QC4
DIV_SELC
1
0
QD0 - QD4
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8701-01
QB1
VDDOB
QB0
QA4
VDDOA
QA3
GND
QA2
GND
QA1
VDDOA
QA0
DIV_SELD
nMR/OE
INV0
INV1
Output
Polarity
Control
DIV_SELA
DIV_SELB
LVCMOS_CLK
GND
VDDI
INV0
GND
INV1
VDDI
nMR/OE
DIV_SELC
DIV_SELD
48-Pin LQFP
Y Package
Top View
8701-01
www.icst.com
1
REV. A - AUGUST 28, 2000
1
2
3
4
5
6
7
8
9
10
