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ICS86953BYIT-147 Datasheet

  • ICS86953BYIT-147

  • DIFFERENTIAL-TO-LVCMOS / LVTTL ZERO DELAY BUFFER

  • 13頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS86953I-147
L
OW
S
KEW
, 1-
TO
-9
D
IFFERENTIAL
-
TO
-LVCMOS / LVTTL Z
ERO
D
ELAY
B
UFFER
F
EATURES
鈥?9 single ended LVCMOS/LVTTL outputs;
(8) clocks, (1) feedback
鈥?PCLK, nPCLK pair can accept the following differential
input levels: LVPECL, CML, SSTL
鈥?Maximum output frequency: PLL Mode, 175MHz
鈥?VCO range: 250MHz to 700MHz
鈥?Output skew: 75ps (maximum)
鈥?Cycle-to-cycle jitter: 50ps (maximum)
鈥?Static phase offset: 90ps 鹵 110ps
鈥?3.3V supply voltage
G
ENERAL
D
ESCRIPTION
The ICS86953I-147 is a low voltage, low skew
1-to-9 Differential-to-LVCMOS/LVTTL Clock
HiPerClockS鈩?/div>
Generator and a member of the HiPerClock 鈩?/div>
S
family of High Performance Clock Solutions from
ICS. The PCLK, nPCLK pair can accept most stan-
dard differential input levels. With output frequencies up to 175MHz,
the ICS86953I-147 is targeted for high performance clock ap-
plications. Along with a fully integrated PLL, the ICS86953I-147
contains frequency configurable outputs and an external feed-
back input for regenerating clocks with 鈥渮ero delay鈥?
ICS
P
IN
A
SSIGNMENT
VCO_SEL
nBYPASS
PLL_SEL
GND
GND
V
DDO
QFB
Q0
鈥?-40擄C to 85擄C ambient operating temperature
鈥?Pin compatible to the MPC953
32 31 30 29 28 27 26 25
V
DDA
FB_CLK
nc
nc
nc
nc
GND
PCLK
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
nPCLK
MR/nOE
V
DDO
Q7
GND
Q6
V
DDO
Q5
24
23
22
Q1
V
DDO
Q2
GND
Q3
V
DDO
Q4
GND
ICS86953I-147
21
20
19
18
17
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
B
LOCK
D
IAGRAM
PCLK
nPCLK
FB_CLK
VCO_SEL
nBYPASS
MR/nOE
PLL_SEL
0
Phase
Detector
0
LPF
VCO
1
梅2
1
梅4
0
1
7
QFB
/
Q0:Q6
Q7
86953BYI-147
www.icst.com/products/hiperclocks.html
1
REV. B APRIL 23, 2004

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