HiPerClockS鈩?/div>
is a member of the HiPerClockS鈩?family of High
Performance Clock Solutions from ICS. The
ICS854058 has 8 selectable differential clock in-
puts. The PCLK, nPCLK input pairs can accept LVPECL, LVDS,
CML or SSTL levels. The fully differential architecture and low
propagation delay make it ideal for use in clock distribution cir-
cuits. The select pins have internal pulldown resistors. The SEL2
pin is the most significant bit and the binary number applied to
the select pins will select the same numbered data input (i.e.,
000 selects PCLK0, nPCLK0).
ICS
B
LOCK
D
IAGRAM
PCLK0
nPCLK0
PCLK1
nPCLK1
PCLK2
nPCLK2
PCLK3
nPCLK3
PCLK4
nPCLK4
PCLK5
nPCLK5
PCLK6
nPCLK6
PCLK7
nPCLK7
P
IN
A
SSIGNMENT
PCLK0
nPCLK0
PCLK1
nPCLK1
V
DD
SEL0
SEL1
SEL2
PCLK2
nPCLK2
PCLK3
nPCLK3
Q0
nQ0
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
000
001
010
011
PCLK7
nPCLK7
PLCK6
nPCLK6
V
DD
Q0
nQ0
GND
PCLK5
nPCLK5
PCLK4
nPCLK4
100
ICS854058
24-Lead, 173-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Top View
101
110
111
SEL2
SEL1 SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
854058AG
www.icst.com/products/hiperclocks.html
REV. A APRIL 8, 2004
1