HiPerClockS鈩?/div>
and a member of the HiPerClockS鈩?family of High
Performance Clock Solutions from ICS. The
ICS8535-01 has two single ended clock inputs.
the single ended clock input accepts LVCMOS or LVTTL in-
put levels and translate them to 3.3V LVPECL levels. The
clock enable is internally synchronized to eliminate runt clock
pulses on the output during asynchronous assertion/
deassertion of the clock enable pin.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8535-01 ideal for those applications demand-
ing well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
CLK0
CLK1
0
1
Q0
nQ0
Q1
nQ1
CLK_SEL
Q2
nQ2
Q3
nQ3
P
IN
A
SSIGNMENT
V
EE
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
ICS8535-01
20-Lead TSSOP
4.4mm x 6.5mm x 0.92mm body package
G Package
Top View
ICS8535AG-01
www.icst.com/products/hiperclocks.html
1
REV. B JULY 5, 2001