HiPerClockS鈩?/div>
family of High Performance Clock Solutions from
ICS. The device has both common select and indi-
vidual select inputs. When COM_SEL is logic High,
the CLKxx input pairs will be passed to the output. When
COM_SEL is logic Low, the output is determined by the setting
of the SEL0 pin for channel 0 and the SEL1 pin for Channel 1.
ICS
The differential input has a common mode range that can accept
most differential input types such as LVPECL, LVDS, LVHSTL,
SSTL, and HCSL. The ICS85356I can therefore be used as a
differential translator to translate almost any differential input type
to LVPECL. It can also be used in ECL mode by setting V
CC
=0V
and V
EE
to -3.0V to - 3.8V.
The ICS85356I adds negligible jitter to the input clock and can
operate at high frequencies in excess of 900MHz thus making
it ideal for use in demanding applications such as SONET,
Fibre Channel, 1 Gigabit/10 Gigabit Ethernet.
鈥?/div>
Translates any single ended input signal to 3.3V
LVPECL levels with resistor bias on nCLKxx input
鈥?/div>
Output skew: 75ps (typical)
鈥?/div>
Propagation delay: 1.15ns (typical)
鈥?/div>
LVPECL mode operating voltage supply range:
V
CC
= 3V to 3.8V, V
EE
= 0V
鈥?/div>
ECL mode operating voltage supply range:
V
CC
= 0V, V
EE
= -3V to -3.8V
鈥?/div>
-40擄C to 85擄C ambient operating temperature
鈥?/div>
Lead-Free package available
鈥?/div>
Compatible with MC100LVEL56
B
LOCK
D
IAGRAM
CLK0A
nCLK0A
CLK0B
nCLK0B
SEL0
COM_SEL
SEL1
0
1
Q0
nQ0
P
IN
A
SSIGNMENT
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
nc
CLK1B
nCLK1B
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
nQ0
SEL0
COM_SEL
SEL1
V
CC
Q1
nQ1
V
EE
CLK0A
nCLK0A
nc
CLK0B
nCLK0B
CLK1A
nCLK1A
nc
CLK1B
nCLK1B
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
Q0
nQ0
SEL0
COM_SEL
SEL1
V
CC
Q1
nQ1
V
EE
ICS85356I
CLK1A
nCLK1A
CLK1B
nCLK1B
0
1
Q1
nQ1
ICS85356I
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
G Package
Top View
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm
M Package
Top View
85356AMI
www.icst.com/products/hiperclocks.html
1
REV. A OCTOBER 7, 2004
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