HiPerClockS鈩?/div>
of the HiPerClockS鈩amily of High Performance
Clock Solutions from ICS. The ICS8534-01 has two
selectable clock inputs. The CLK, nCLK pair can
accept most standard differential input levels. The PCLK, nPCLK
pair can accept LVPECL, CML, or SSTL input levels. The de-
vice is internally synchronized to eliminate runt pulses on the
outputs during asynchronous assertion/deassertion of the OE
pin. The ICS8534-01鈥檚 low output and part-to-part skew char-
acteristics make it ideal for workstation, server, and other high
performance clock distribution applications.
ICS
B
LOCK
D
IAGRAM
CLK_SEL
CLK
nCLK
PCLK
nPCLK
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
25
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
V
CCO
nQ13
Q13
nQ12
Q12
nQ11
Q11
nQ10
Q10
nQ9
Q9
nQ8
Q8
nQ7
Q7
V
CCO
0
22
22
Q0:Q21
nQ0:nQ21
1
LE
Q
OE
D
V
CCO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
CCO
ICS8534-01
V
CCO
Q14
nQ14
Q15
nQ15
Q16
nQ16
Q17
nQ17
Q18
nQ18
Q19
nQ19
Q20
nQ20
V
CCO
8534AY-01
www.icst.com/products/hiperclocks.html
1
V
CCO
nc
nc
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
OE
nc
nc
nQ21
Q21
V
CCO
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
Top View
REV. A NOVEMBER 19, 2004