Fanout Buffer and a member of the HiPerClockS鈩?/div>
family of High Performance Clock Solutions from
ICS. The ICS853031 has two selectable clock in-
puts. The CLK, nCLK pair can accept most standard differential
input levels. The PCLK, nPCLK pair can accept LVPECL, LVDS,
CML, or SSTL input levels. The clock enable is internally syn-
chronized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin.
ICS
Guaranteed output skew and part-to-part skew characteristics
make the ICS853031 ideal for high performance workstation
and server applications.
B
LOCK
D
IAGRAM
CLK_EN
P
IN
A
SSIGNMENT
V
CCO
V
CCO
nQ0
nQ1
nQ2
Q0
Q1
Q2
D
Q
LE
32 31 30 29 28 27 26 25
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q8
nQ8
V
CC
CLK
nCLK
CLK_SEL
PCLK
nPCLK
V
EE
CLK_EN
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Vcco
nQ8
Q8
nQ7
Q7
nQ6
Q6
Vcco
CLK
nCLK
PCLK
nPCLK
0
1
24
23
22
21
20
19
18
17
V
CCO
Q3
nQ3
Q4
nQ4
Q5
nQ5
V
CCO
CLK_SEL
ICS853031
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
853031AY
www.icst.com/products/hiperclocks.html
1
REV. B SEPTEMBER 16, 2004