HiPerClockS鈩?/div>
member of the HiPerClockS鈩?family of High
Performance Clock Solutions from ICS. The
ICS8525 has two selectable clock inputs that ac-
cept LVCMOS or LVTTL input levels and translate them to
1.8V LVHSTL levels. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8525 ideal for those applications demanding
well defined performance and repeatability.
B
LOCK
D
IAGRAM
CLK_EN
D
Q
LE
CLK0
CLK1
0
1
Q0
nQ0
Q1
nQ1
CLK_SEL
Q2
nQ2
Q3
nQ3
P
IN
A
SSIGNMENT
GND
CLK_EN
CLK_SEL
CLK0
nc
CLK1
nc
nc
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
DDO
Q1
nQ1
Q2
nQ2
V
DDO
Q3
nQ3
ICS8525
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm Package Body
G Package
Top View
8525BG
www.icst.com/products/hiperclocks.html
1
REV. B JULY 27, 2001