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ICS8524AYT Datasheet

  • ICS8524AYT

  • LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER

  • 314.57KB

  • 17頁(yè)

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS8524
L
OW
S
KEW
, 1-
TO
-22
D
IFFERENTIAL
-
TO
-HSTL F
ANOUT
B
UFFER
F
EATURES
鈥?/div>
22 differential HSTL outputs
each with the ability to drive 50鈩?to ground
鈥?/div>
Selectable differential CLK, nCLK or LVPECL clock inputs
鈥?/div>
CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, HSTL, SSTL, HCSL
鈥?/div>
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
鈥?/div>
Maximum output frequency: 500MHz
鈥?/div>
Translates any single-ended input signal (LVCMOS, LVTTL,
GTL) to HSTL levels with resistor bias on nCLK input
鈥?/div>
Output skew: 80ps (maximum)
鈥?/div>
Part-to-part skew: 700ps (maximum)
鈥?/div>
Jitter, RMS: 0.04ps (typical)
鈥?/div>
LVPECL and HSTL mode operating voltage supply range: V
DD
= 3.3V 鹵 5%, V
DDO
= 1.6V to 2V, GND = 0V
鈥?/div>
0擄C to 85擄C ambient operating temperature
鈥?/div>
Pin compatible with the SY89824L and NB100EP223
G
ENERAL
D
ESCRIPTION
The ICS8524 is a low skew, 1-to-22 Differential-
to-HSTL Fanout Buffer and a member of the
HiPerClockS鈩?/div>
HiPerClockS鈩amily of High Performance Clock
Solutions from ICS. The ICS8524 has two select-
able clock inputs. The CLK, nCLK pair can accept
most standard differential input levels. The PCLK, nPCLK pair
can accept LVPECL, CML, or SSTL input levels. The device is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the OE pin. The
ICS8524鈥檚 low output and part-to-part skew characteristics
make it ideal for workstation, server, and other high performance
clock distribution applications.
ICS
B
LOCK
D
IAGRAM
CLK_SEL
CLK
nCLK
PCLK
nPCLK
P
IN
A
SSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
49
32
50
31
51
30
52
29
53
28
54
27
55
26
56
25
57
24
58
23
59
22
60
21
61
20
62
19
63
18
64
17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
V
DDO
nQ13
Q13
nQ12
Q12
nQ11
Q11
nQ10
Q10
nQ9
Q9
nQ8
Q8
nQ7
Q7
V
DDO
0
22
22
Q0:Q21
nQ0:nQ21
1
LE
Q
OE
D
V
DDO
nQ6
Q6
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
V
DDO
ICS8524
V
DDO
Q14
nQ14
Q15
nQ15
Q16
nQ16
Q17
nQ17
Q18
nQ18
Q19
nQ19
Q20
nQ20
V
DDO
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
Top View
8524AY
www.icst.com/products/hiperclocks.html
1
V
DDO
nc
nc
V
DD
CLK
nCLK
CLK_SEL
PCLK
nPCLK
GND
OE
nc
nc
nQ21
Q21
V
DDO
REV. B SEPTEMBER 18, 2003

ICS8524AYT相關(guān)型號(hào)PDF文件下載

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