HiPerClockS鈩?/div>
and a member of the HiPerClockS鈩?family of
High Performance Clock Solutions from ICS. The
ICS8520 has 1 clock input pair. The CLK, nCLK
pair can accept most standard differential input levels.
,&6
Guaranteed output skew, part-to-part skew and crossover
voltage characteristics make the ICS8520 ideal for interfac-
ing to today鈥檚 most advanced microprocessor and static
RAMs.
B
LOCK
D
IAGRAM
CLK
nCLK
P
IN
A
SSIGNMENT
nCLK
VCCO
Q15
nQ15
Q14
nQ14
GND
Q13
nQ13
Q12
nQ12
VCCO
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
Q7
nQ7
Q15
nQ15
Q14
nQ14
Q13
nQ13
Q12
nQ12
Q11
nQ11
Q10
nQ10
Q9
nQ9
Q8
nQ8
VCCO
Q11
nQ11
Q10
nQ10
GND
Q9
nQ9
Q8
nQ8
VCCO
VCC
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8520
CLK
VCCO
nQ0
Q0
nQ1
Q1
GND
nQ2
Q2
nQ3
Q3
VCCO
48-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
ICS8520DY
www.icst.com/products/hiperclocks.html
REV. B JULY 5, 2001
1
VCCO
nQ4
Q4
nQ5
Q5
GND
nQ6
Q6
nQ7
Q7
VCCO
VCC