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ICS84321AY Datasheet

  • ICS84321AY

  • 260MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHE...

  • 204.34KB

  • 18頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS84321
260MH
Z
, C
RYSTAL
-
TO
-3.3V D
IFFERENTIAL
LVPECL F
REQUENCY
S
YNTHESIZER
F
EATURES
鈥?/div>
Dual differential 3.3V LVPECL outputs
鈥?/div>
Selectable crystal oscillator interface
or LVCMOS/LVTTL TEST_CLK
鈥?/div>
Output frequency range: 103.3MHz to 260MHz
鈥?/div>
Crystal input frequency range: 14MHz to 40MHz
鈥?/div>
VCO range: 620MHz to 780MHz
鈥?/div>
Parallel or serial interface for programming counter
and output dividers
鈥?/div>
RMS period jitter: 3ps (typical)
鈥?/div>
RMS phase jitter at 155.52MHz, using a 38.88MHz crystal
(12kHz to 20MHz): 2.5ps (typical)
Phase noise: 155.52MHz
Offset
Noise Power
100Hz .................. -84.1 dBc/Hz
1kHz ................ -109.8 dBc/Hz
10kHz ................ -126.3 dBc/Hz
100kHz ................ -128.7 dBc/Hz
鈥?/div>
3.3V supply voltage
鈥?/div>
0擄C to 70擄C ambient operating temperature
鈥?/div>
Lead-Free package RoHS compliant
G
ENERAL
D
ESCRIPTION
The ICS84321 is a general purpose, dual output
Crystal-to-3.3V Differential LVPECL High Frequency
HiPerClockS鈩?/div>
Synthesizer and a member of the HiPerClockS鈩?/div>
family of High Performance Clock Solutions from
ICS. The ICS84321 has a selectable TEST_CLK or
crystal inputs. The VCO operates at a frequency range of 620MHz
to 780MHz. The VCO frequency is programmed in steps equal
to the value of the input reference or crystal frequency. The VCO
and output frequency can be programmed using the serial or
parallel interfaces to the configuration logic.
ICS
B
LOCK
D
IAGRAM
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
OSC
XTAL_OUT
0
P
IN
A
SSIGNMENT
VCO_SEL
nP_LOAD
XTAL_IN
M4
M3
M2
M1
M0
32 31 30 29 28 27 26 25
1
M5
M6
M7
M8
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
TEST
V
CC
FOUT1
nFOUT1
V
CCO
FOUT0
nFOUT0
V
EE
24
23
22
XTAL_OUT
TEST_CLK
XTAL_SEL
V
CCA
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
梅
M
VCO
0
1
梅
梅
梅
梅
3
4
5
6
N0
N1
nc
FOUT0
nFOUT0
FOUT1
nFOUT1
V
EE
ICS84321
21
20
19
18
17
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
M0:M8
N0:N1
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
84321AY
www.icst.com/products/hiperclocks.html
1
REV. B JUNE 9, 2005

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