HiPerClockS鈩?/div>
a member of the HiPerClockS鈩?family of High
Performance Clock Solutions from ICS. The
ICS8431-01 consists of one independent low
bandwidth PLL timing channel. A 16.666MHz crystal is used
as the input to the on-chip oscillator. The M is configured to
produce a fixed output frequency of 200MHz.
,&6
Programmable features of the ICS8431-01 support four
operational modes. The four modes are spread spectrum
clocking (SSC), non-spread spectrum clock and two test
modes which are controlled by the SSC_CTL[1:0] pins. Un-
like other synthesizers, the ICS8431-01 can immediately
change spread-spectrum operation without having to reset
the device.
In SSC mode, the output clock is modulated in order to
achieve a reduction in EMI. In one of the PLL bypass test
modes, the PLL is disconnected as the source to the
differential output allowing an external source to be
connnected to the TEST_I/O pin. This is useful for in-
circuit testing and allows the differential output to be driven
at a lower frequency throughout the system clock tree. In the
other PLL bypass mode, the oscillator divider is used as the
source to both the M and the Fout divide by 2. This is useful
for characterizing the oscillator and internal dividers.
B
LOCK
D
IAGRAM
XTAL1
OSC
XTAL2
梅
16
P
IN
A
SSIGNMENT
nc
nc
nc
nc
nc
nc
nc
nc
nc
SSC_CTL0
SSC_CTL1
VEE
TEST_I/O
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
nc
VDDI
XTAL2
XTAL1
nc
nc
VDDA
VEE
RESERVED
nc
VDDO
FOUT
nFOUT
VEE
PLL
PHASE
DETECTOR
VCO
梅
M
梅
2
FOUT
nFOUT
TEST_I/O
SSC_CTL0
SSC_CTL1
SSC
Control
Logic
ICS8431-01
28-Lead SOIC
M Package
Top View
ICS8431CM-01
www.icst.com/products/hiperclocks.html
1
REV. A JUNE 5, 2001