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ICS8344BYI-T Datasheet

  • ICS8344BYI-T

  • LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER

  • 16頁

  • ICS

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Integrated
Circuit
Systems, Inc.
ICS8344I
L
OW
S
KEW
, 1-
TO
-24
D
IFFERENTIAL
-
TO
-LVCMOS F
ANOUT
B
UFFER
F
EATURES
鈥?/div>
24 LVCMOS outputs, 7鈩?typical output impedance
鈥?/div>
2 selectable differential clock input pairs for redundant clock
applications
鈥?/div>
CLKx, nCLKx pair can accept the following differential input
levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
鈥?/div>
Maximum output frequency up to 100MHz
鈥?/div>
Translates any single-ended input signal to LVCMOS with
resistor bias on nCLK input
鈥?/div>
Multiple output enable pins for disabling unused outputs in
reduced fanout applications
鈥?/div>
Output skew: 275ps (maximum)
鈥?/div>
Part-to-part skew: 600ps (maximum)
鈥?/div>
Bank skew: 150ps (maximum)
鈥?/div>
3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
鈥?/div>
-40擄C to 85擄C ambient operating temperature
G
ENERAL
D
ESCRIPTION
The ICS8344I is a low voltage, low skew fanout
buffer and a member of the HiPerClockS鈩?/div>
HiPerClockS鈩?/div>
family of High Performance Clock Solutions from
ICS. The ICS8344I has two selectable clock in-
puts. The CLK0, nCLK0 and CLK1, nCLK1 pairs
can accept most standard differential input levels. The
ICS8344I is designed to translate any differential signal lev-
els to LVCMOS levels. The low impedance LVCMOS outputs
are designed to drive 50鈩?series or parallel terminated trans-
mission lines. The effective fanout can be increased to 48 by
utilizing the ability of the outputs to drive two series termi-
nated lines. Redundant clock applications can make use of
the dual clock input. The dual clock inputs also facilitate board
level testing. ICS8344I is characterized at full 3.3V, full 2.5V
and mixed 3.3V input and 2.5V output operating supply modes.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8344I ideal for those clock distribution applica-
tions demanding well defined performance and repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
Q8
Q9
V
DDO
GND
Q10
Q11
Q12
Q13
V
DDO
GND
Q14
Q15
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
Q16
Q17
V
DDO
GND
Q18
Q19
Q20
Q21
V
DDO
GND
Q22
Q23
0
1
Q0 - Q7
OE1
Q8 - Q15
OE2
Q16 - Q23
OE3
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8344I
Q7
Q6
V
DDO
GND
Q5
Q4
Q3
Q2
V
DDO
GND
Q1
Q0
48-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8344BYI
www.icst.com/products/hiperclocks.html
1
OE1
OE2
OE3
CLK0
nCLK0
V
DD
GND
CLK1
nCLK1
V
DD
GND
CLK_SEL
REV. A AUGUST 9, 2001

ICS8344BYI-T相關(guān)型號PDF文件下載

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  • 英文版
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  • 英文版
    LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
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  • 英文版
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