ICS. The ICS8344-01 is designed to translate any
differential signal levels to LVCMOS levels. The
low impedance LVCMOS outputs are designed to drive 50鈩?/div>
series or parallel terminated transmission lines. The effective
fanout can be increased to 48 by utilizing the ability of the
outputs to drive two series terminated lines. Redundant clock
applications can make use of the dual clock input. The dual
clock inputs also facilitate board level testing. The output
enable is synchronous which eliminates the runt clock pulses
which occur during asynchronous enabling and disabling of
the outputs. The outputs are driven low when disabled. The
ICS8344-01 is characterized at full 3.3V, full 2.5V and mixed
3.3V input and 2.5V output operating supply modes.
,&6
Guaranteed output and part-to-part skew characteristics
make the ICS8344-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
Q8
Q9
VDDO
GND
Q10
Q11
Q12
Q13
VDDO
GND
Q14
Q15
CLK_SEL
CLK0
nCLK0
CLK1
nCLK1
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
0
1
Q0 - Q7
O8 - Q15
O16 - Q23
LE
Q
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
ICS8344-01
Q7
Q6
VDDO
GND
Q5
Q4
Q3
Q2
VDDO
GND
Q1
Q0
nc
OE
CLK_EN
CLK0
nCLK0
VDDI
GND
CLK1
nCLK1
VDDI
GND
CLK_SEL
CLK_EN
nD
OE
48-Lead LQFP
Y Package
Top View
8344-01
www.icst.com
1
REV. A JANUARY 30, 2001