ICS663
PLL B
UILDING
B
LOCK
Description
The ICS663 is a low cost Phase-Locked Loop (PLL)
designed for clock synthesis and synchronization.
Included on the chip are the phase detector, charge
pump, Voltage Controlled Oscillator (VCO) and an
output buffer. Through the use of external reference
and VCO dividers (implemented with the ICS674-01,
for example), the user can easily configure the device
to lock to a wide variety of input frequencies.
The phase detector and VCO functions of the device
can also be used independently. This enables the
configuration of other PLL circuits. For example, the
ICS663 phase detector can be used to control a VCXO
circuit such as the MK3754.
For applications requiring Power Down or Output
Enable features, please refer to the ICS673-01.
Features
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Packaged in 8-pin SOIC
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Output clock range 1 MHz to 100 MHz (3.3 V), 1 MHz
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to 120 MHz (5 V)
External PLL loop filter enables configuration for a
wide range of input frequencies
(video Hsync, for example)
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Ability to accept an input clock in the kHz range
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25 mA output drive capability at TTL levels
Lower power CMOS process
+3.3 V 鹵5% or +5 V 鹵10% operating voltage
Used along with the ICS674-01, forms a complete
PLL circuit
independently for other PLL configurations
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Phase detector and VCO blocks can be used
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Industrial temperature version available
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For better jitter performance, use the MK1575
Block Diagram
LF
LFR
VDD
I
cp
C lock Input
R E FIN
P hase/
Frequency
D etector
UP
F B IN
VCO
DOWN
1
MUX
4
0
2
C LK
I
cp
SEL
External Feedback D ivider
(such as the IC S674-01)
MDS 663 D
I n t e gra te d C i r c u i t S y s t e m s
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1
525 Race Stre et, San Jo se, CA 9 5126
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Revision 062904
te l (40 8) 2 97-12 01
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w w w. i c st . c o m
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