PRELIMINARY INFORMATION
ICS627-01
HDTV Set-Top Clock Source
Description
The ICS627-01 is a low cost, low jitter, high
performance clock synthesizer which can generate
frequencies required for HDTV receivers and set-
top boxes. Using ICS鈥檚 patented analog/digital
Phase-Locked Loop (PLL) techniques, the device
uses an inexpensive fundamental 27 MHz crystal
input to produce low jitter HDTV pixel clocks. It
has a separate input for a 1001/1000 or
2(1001/1000) conversion from a 13.5 MHz,
27 MHz or 54 MHz input.
Features
鈥?Packaged in 28 pin SSOP (QSOP)
鈥?HDTV frequencies of 74.25 and 74.175824 MHz
鈥?Provides selectable B clock for 27.027 MHz or
other 1001/1000
鈥?Uses a fundamental 27 MHz crystal or clock input
鈥?All frequencies are generated exactly (zero ppm
synthesis error)
鈥?Full CMOS output swings with 12 mA output
drive capability at TTL levels
鈥?Advanced, low power, sub-micron CMOS process
鈥?3.3 V 鹵5% operating supply
Block Diagram
VDD
GND
CLKIN
SB
x1001/1000
PLL
Output
Buffer
CLKB
SA2:0
6
PLL
Clock
Synthesis
Circuitry
梅2
Output
Buffer
Output
Buffer
CLKA
CLKC
(54 MHz)
X1/ICLK
27.0 MHz
crystal or
X2
clock
input
Crystal
Oscillator
Output
Buffer
Output
Buffer
CLKC/2
(27 MHz)
REFOUT
(27 MHz)
MDS 627-01 B
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Revision 051600
Integrated Circuit Systems, Inc. 鈥?525 Race Street 鈥?San Jose 鈥A鈥?5126鈥?408) 295-9800tel 鈥?www.icst.com
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