that require low phase noise and low jitter. It is
lowest CMOS part in the industry. Using ICS鈥?/div>
patented analog and digital Phase Locked Loop
(PLL) techniques, the chip accepts a 10-27 MHz
crystal or clock input, and produces output clocks
up to 156 MHz at 3.3 V.
Features
鈥?Packaged in 16 pin SOIC or TSSOP
鈥?Uses fundamental 10 - 27 MHz crystal, or clock
鈥?Patented PLL with the lowest phase noise
鈥?Output clocks up to 156 MHz at 3.3 V
鈥?Low phase noise: -132 dBc/Hz at 10 kHz
鈥?Output Enable function tri states outputs
鈥?Low jitter - 18 ps one sigma
鈥?Full swing CMOS outputs with 25 mA drive
capability at TTL levels
鈥?Advanced, low power, sub-micron CMOS process
鈥?Industrial temperature version available
鈥?3.3 V or 5 V operation
Block Diagram
VDD
Reference
Divide
X1/ICLK
Phase
Comparator
Charge
Pump
Loop
Filter
VCO
Output
Buffer
CLK
Crystal
Oscillator
X2
VCO
Divide
ROM Based
Multipliers
Output
Buffer
REFOUT
GND
S3 S2 S1 S0
OE
REFEN
1
Revision 090800
Printed 11/14/00
Integrated Circuit Systems, Inc. 鈥?525 Race Street 鈥?San Jose 鈥A鈥?5126鈥?(408) 295-9800tel 鈥?www.icst.com
MDS 601-01 G