PRELIMINARY INFORMATION
ICS571
Low Phase Noise Zero Delay Buffer
Features
鈥?Packaged in 8 pin SOIC.
鈥?Can function as low phase noise x2 multiplier.
鈥?Low skew outputs. One is 梅2 of other.
鈥?Input clock frequency up to 160 MHz at 3.3V.
鈥?Phase noise of better than -100 dBc/Hz from
1kHz to 1MHz offset from carrier
鈥?Can recover poor input clock duty cycle.
鈥?Output clock duty cycle of 45/55 at 3.3V.
鈥?High drive strength for >100 MHz outputs.
鈥?Full CMOS clock swings with 25mA drive
capability at TTL levels.
鈥?Advanced, low power CMOS process.
鈥?Operating voltages of 3.0 to 5.5 V.
Description
The ICS571 is a high speed, high output drive, low
phase noise Zero Delay Buffer (ZDB) which
integrates ICS鈥?proprietary analog/digital Phase
Locked Loop (PLL) techniques. ICS introduced
the world standard for these devices in 1992 with
the debut of the AV9170, and updated that with
the ICS570. The ICS571, part of ICS鈥?/div>
ClockBlocks
鈩?/div>
family, was designed to operate at
higher frequencies, with faster rise and fall times,
and with lower phase noise. The zero delay feature
means that the rising edge of the input clock aligns
with the rising edges of both outputs, giving the
appearance of no delay through the device. There
are two outputs on the chip, one being a low-skew
divide by two of the other.
The chip is ideal for synchronizing outputs in a
large variety of systems, from personal computers
to data communications to video. By allowing off-
chip feedback paths, the ICS571 can eliminate the
delay through other devices. The use of dividers in
the feedback path will enable the part to multiply
by more than two.
Block Diagram
ICLK
FBIN
Phase
Detector,
Charge
Pump, and
Loop Filter
Voltage
Controlled
Oscillator
梅2
Output
Buffer
CLK
Output
Buffer
CLK/2
External feedback can come from CLK or CLK/2 (see table on page 2).
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Revision 072899
Printed 11/14/00
Integrated Circuit Systems, Inc.鈥?25 Race Street鈥an Jose鈥A鈥?5126鈥?408)295-9800tel鈥?408)295-9818fax
MDS 571 B
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