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Packaged in 16-pin TSSOP
Available in Pb (lead) free package
Supports LVDS Output Levels
Operating voltage of 3.3 V
Input frequency of 25 MHz
Outputs (HCSL, 0.7 V Current mode differential pair)
Jitter 100 ps (peak-to-peak)
Spread of 鹵0.25%, -0.5%, -0.75%, and no spread.
Industrial and commercial temperature ranges
Block Diagram
VDD
2
SS1:SS0
S1:S0
2
CLK0
Control
Logic
Phase Lock Loop
CLK1
CLK1
CLK0
2
X1/ICLK
25 MHz
crystal or clock X2
Optional tuning crystal
capacitors
Clock
Buffer/
Crystal
Oscillator
2
GND
OE
Rr(IREF)
MDS 557-03 E
I n t e gra te d C i r c u i t S y s t e m s
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1
525 Race Stre et, San Jo se, CA 9 5126
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Revision 061005
te l (40 8) 2 97-12 01
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