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ICS507-XX Datasheet

  • ICS507-XX

  • PECL Clock Synthesizer

  • 53.61KB

  • 5頁

  • ICS

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ICS507-01/02
PECL Clock Synthesizer
Description
The ICS507-01 and ICS507-02 are inexpensive
ways to generate a low jitter 155.52 MHz (or other
high speed) differential PECL clock output from a
low frequency crystal input. Using Phase-Locked-
Loop (PLL) techniques, the devices use a standard
fundamental mode crystal to produce output
clocks up to 200 MHz.
Stored in each chip鈥檚 ROM is the ability to
generate a selection of different multiples of the
input reference frequency, including an exact
155.52 MHz clock from common crystals. For
lowest jitter and phase noise on a 155.52 MHz
clock, a 19.44 MHz crystal and the x8 selection
can be used.
Features
鈥?Packaged as 16 pin narrow SOIC or die
鈥?Input crystal frequency of 5 - 27 MHz
鈥?Input clock frequency of 5 - 52 MHz
鈥?Uses low-cost crystal
鈥?Differential PECL output clock frequencies up
to 200 MHz
鈥?Duty cycle of 49/51
鈥?3.3 V or 5.0 V鹵10% operating supply
鈥?Ideal for SONET applications and oscillator
manufacturers
鈥?Advanced, low power CMOS process
鈥?Industrial temperature versions available
Block Diagram
GND
VDD
1.1k鈩?/div>
RES
270鈩?/div>
S0:1
2
Clock Synthesis
and Control
Circuitry
Clock
Buffer/
Crystal
Oscillator
Output
Buffer
62鈩?/div>
PECL
VDD
62鈩?/div>
Crystal
or
clock
X1
Output
Buffer
PECL
270鈩?/div>
X2
Output resistor values shown are for unterminated lines.
Refer to MAN09 for additional information.
Output Enable
(both outputs)
1
Revision 042600
Printed 11/13/00
Integrated Circuit Systems, Inc. 鈥?525 Race Street 鈥?San Jose 鈥A 鈥?5126鈥?(408)295-9800tel 鈥?www.icst.com
MDS 507 C

ICS507-XX相關(guān)型號PDF文件下載

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