ICS1892Y-14 Datasheet

IC型號(hào)：
ICS1892Y-14
PDF描述：
10Base-T/100Base-TX Integrated PHYceiver
文件大小：
756.68KB
PDF頁數(shù)：
148頁
芯片廠家：
ICS

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Integrated Circuit Systems, Inc.

ICS1892

10Base-T/100Base-TX Integrated PHYceiver錚?/div>

General

The ICS1892, an enhanced version of the ICS 1890, is a

fully integrated, physical-layer device (PHY) that is

compliant with both the 10Base-T and 100Base-TX

CSMA/CD Ethernet Standard, ISO/IEC 8802-3.

The ICS1892 incorporates digital signal processing (DSP)

in its Physical Medium Dependent (PMD) sublayer. As a

result, it can transmit and receive data on unshielded

twisted-pair (UTP) category 5 cable with attenuation in

excess of 24 dB at 100 MHz. With this ICS-patented

technology, the ICS1892 can virtually eliminate errors from

killer packets.

The ICS1892 supports a broad range of applications: data

terminal equipm ent (netwo rk in terf ace card s and

motherboards), switches, repeaters, bridges, and routers. Its

Media Independent Interface (MII) supports direct

c h i p - t o - c h i p a n d m o t h e r b o a r d - t o - d a u g h t e r b o ar d

connections as well as connections to an MII connector and

cable. The ICS1892 also provides a Serial Management

Interface for exchanging command and status information

with a Station Management (STA) entity.

The ICS1892 Media Dependent Interface (MDI) can be

configured to provide either half- or full-duplex operation at

data rates of 10 MHz or 100 MHz. The MDI configuration

can be done manually (with input pins or control register

settings) or automatically (using the Auto-Negotiation

features). When the ICS1892 Auto-Negotiation sublayer is

enabled, it exchanges technology capability data with its

remote link partner and automatically selects the

highest-performance operating mode they have in common.

ICS1892 Block Diagram

100Base-T

10/100 MII or

Alternate

MAC/Repeater

Interface

MUX

PCS

鈥?Frame

鈥?CRS/COL

Detection

鈥?Parallel to Serial

鈥?4B/5B

PMA

鈥?Clock Recovery

鈥?Link Monitor

鈥?Signal Detection

鈥?Error Detection

Document Type:

Data Sheet

Document Stage: Released

Features

鈥?/div>

Supports category 5 cables with attenuation in excess of

鈥?/div>

24 dB at 100 MHz across a temperature range from -5擄 to

+85擄 C

DSP-based baseline wander correction to virtually

eliminate killer packets across temperature range of from

-5擄 to +85擄 C

Low-power, 0.5-micron CMOS

Single 5.0-V power supply.

Single-chip, fully integrated PHY provides PCS, PMA,

PMD, and AUTONEG sublayers of IEEE standard

10Base-T and 100Base-TX IEEE 802.3 compliant

Fully integrated, DSP-based PMD includes:

鈥?Adaptive equalization and baseline wander correction

鈥?Transmit wave shaping and stream cipher scrambler

鈥?MLT-3 encoder and NRZ/NRZI encoder

鈥?/div>

Node, repeater, and switch applications

Managed and unmanaged applications

10M or 100M half- and full-duplex modes

Parallel detection

Auto-negotiation, with Next Page capabilities

鈥?/div>

Highly configurable design supports:

鈥?/div>

MAC/Repeater Interface can be configured as:

鈥?10M or 100M Media Independent Interface

鈥?100M Symbol Interface (bypasses the PCS)

鈥?10M 7-wire Serial Interface

鈥?/div>

Provides Loopback Modes for Diagnostic Functions

鈥?/div>

Small Footprint 64-pin Low-Profile LQFP and MQFP

packages available

TP_PMD

鈥?MLT-3

鈥?Stream Cipher

鈥?Adaptive Equalizer

鈥?Baseline Wander

Correction

Integrated

Switch

10Base-T

MII

Extended

Set

Low-Jitter

Clock

Synthesizer

Clock

Power

Twisted-

Pair

Interface to

Magnetics

Modules and

RJ45

Connector

MII Serial

Management

Interface

Configuration

and Status

Auto-

Negotiation

LEDs and PHY

Address

1892 Rev. D, 2/26/01

ICS reserves the right to make changes in the device data identified in

this publication without further notice. ICS advises its customers to

obtain the latest version of all device data to verify that any information

being relied upon by the customer is current and accurate.

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