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IC62C1024-35WI Datasheet

  • IC62C1024-35WI

  • 128K X 8 HIGH SPEED CMOS STATIC RAM

  • 8頁(yè)

  • ICSI

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.EATURES
128K x 8 HIGH-SPEED CMOS STATIC RAM
聲 High-speed access time: 35, 45, 55, 70 ns
聲
Low active power: 450 mW (typical)
聲
Low standby power: 500 碌W (typical) CMOS
standby
聲 Output Enable (OE) and two Chip Enable
(CE1 and CE2) inputs for ease in applications
聲 .ully static operation: no clock or refresh
required
聲 TTL compatible inputs and outputs
聲 Single 5V (鹵10%) power supply
DESCRIPTION
The
1+51
IC62C1024 is a low power,131,072-word by 8-bit
CMOS static RAM. It is fabricated using
1+51
's high-
performance CMOS technology. This highly reliable process
coupled with innovative circuit design techniques, yields higher
performance and low power consumption devices.
When
CE1
is HIGH or CE2 is LOW (deselected), the device
assumes a standby mode at which the power dissipation can
be reduced by using CMOS input levels.
Easy memory expansion is provided by using two Chip Enable
inputs,
CE1
and CE2. The active LOW Write Enable (WE)
controls both writing and reading of the memory.
The IC62C1024 is available in 32-pin 600mil DIP, 450mil SOP
and 8*20mm TSOP-1 packages.
.UNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
512 x 2048
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE1
CE2
OE
WE
CONTROL
CIRCUIT
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. 漏 Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
ALSR005-0A
1

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