音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

IBMN364164CT3C-260 Datasheet

  • IBMN364164CT3C-260

  • x16 SDRAM

  • 71頁

  • ETC

掃碼查看芯片數(shù)據(jù)手冊

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

.
IBMN364164 IBMN364804
IBMN364404
64Mb Synchronous DRAM - Die Revision C
Features
鈥?High Performance:
-68 -75A, -260, -360,
Units
CL=3 CL=3 CL=2 CL=3
f
CK
Clock Frequency
t
CK
Clock Cycle
t
AC
Clock Access Time
1
t
AC
Clock Access Time
2
150
6.67
6
133
7.5
鈥?/div>
5.4
100
10
鈥?/div>
6
100
10
鈥?/div>
6
MHz
ns
ns
ns
鈥?Programmable Wrap: Sequential or Interleave
鈥?Multiple Burst Read with Single Write Option
鈥?Automatic and Controlled Precharge Command
鈥?Data Mask for Read/Write control (x4, x8)
鈥?Dual Data Mask for byte control (x16)
鈥?Auto Refresh (CBR) and Self Refresh
鈥?Suspend Mode and Power Down Mode
鈥?Standard or Low Power operation
鈥?4096 refresh cycles/64ms
鈥?Random Column Address every CLK (1-N Rule)
鈥?Single 3.3V
鹵
0.3V Power Supply
鈥?LVTTL compatible
鈥?Package: 54-pin 400 mil TSOP-Type II
鈥?/div>
1. Terminated load. See AC Characteristics on page 40.
2. Unterminated load. See AC Characteristics on page 40.
鈥?Single Pulsed RAS Interface
鈥?Fully Synchronous to Positive Clock Edge
鈥?Four Banks controlled by A12/A13 (Bank Select)
鈥?Programmable CAS Latency: 2, 3
鈥?Programmable Burst Length: 1, 2, 4, 8, full-page
Description
The IBMN364404, IBMN364804, and IBMN364164
are four-bank Synchronous DRAMs organized as
4Mbit x 4 I/O x 4 Bank, 2Mbit x 8 I/O x 4 Bank, and
1Mbit x 16 I/O x 4 Bank, respectively. These syn-
chronous devices achieve high-speed data transfer
rates of up to 150MHz by employing a pipeline chip
architecture that synchronizes the output data to a
system clock. The chip is fabricated with IBM鈥檚
advanced 64Mbit single transistor CMOS DRAM
process technology.
The device is designed to comply with all JEDEC
standards set for synchronous DRAM products,
both electrically and mechanically. All of the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CLK). Internal chip operating modes
are defined by combinations of these signals and a
command decoder initiates the necessary timings
for each operation. A fourteen bit address bus
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
and two bank select addresses (A12, A13) are
strobed with RAS. Ten column addresses (A0-A9)
plus bank select addresses and A10 are strobed
with CAS. Column address A9 is dropped on the x8
device and column addresses A8 and A9 are
dropped on the x16 device.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A9
during a mode register set cycle. In addition, it is
possible to program a multiple burst sequence with
single write cycle for write through cache operation.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 150MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Auto Refresh (CBR),
Self Refresh, and Low Power operation are sup-
ported.
19L3265.E35856B
1/01
漏IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 71

IBMN364164CT3C-260相關(guān)型號PDF文件下載

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時間周一至周五
9:00-17:30

關(guān)注官方微信號，
第一時間獲取資訊。

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務(wù)的動力！意見一經(jīng)采納，將有感恩紅包奉上哦！