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IBM13M16734JCA-360T Datasheet

  • IBM13M16734JCA-360T

  • x72 SDRAM Module

  • 313.66KB

  • 20頁

  • ETC

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IBM13M16734JCA
16M x 72 1 Bank Registered/Buffered SDRAM Module
Features
鈥?168-Pin Registered 8-Byte Dual In-Line Memory
Module
鈥?16Mx72 Synchronous DRAM DIMM
鈥?Performance:
Device Latency
Clock Frequency
Clock Access Time
-260 -360 -360 Units
2
2
3
100
66
100 MHz
7.2
10.2
7.2
ns
鈥?Intended for 66/100MHz and PC100 applica-
tions
鈥?Inputs and outputs are LVTTL (3.3V) compatible
鈥?Single 3.3V
鹵
0.3V Power Supply
鈥?Single Pulsed RAS interface
鈥?SDRAMs have four internal banks
鈥?Module has one physical bank
鈥?Fully Synchronous to positive Clock Edge
鈥?Programmable Operation:
- DIMM CAS Latency:3, 4 (Registered
mode),
2, 3 (Buffered mode)
- Burst Type: Sequential or Interleave
- Burst Length: 1, 2, 4, 8, Full-Page (Full-
Page supports Sequential burst only)
- Operation: Burst Read and Write
or Multiple Burst Read with Single Write
鈥?Data Mask for Byte Read/Write control
鈥?Auto Refresh (CBR) and Self Refresh
鈥?Automatic and controlled Precharge Commands
鈥?Suspend Mode and Power Down Mode
鈥?12/10/2 Addressing (Row/Column/Bank)
鈥?4096 refresh cycles distributed across 64ms
鈥?Card size: 5.25" x 1.5" x 0.157"
鈥?Gold contacts
鈥?SDRAM
S
in TSOP - Type II Package
鈥?Serial Presence Detect with Write protect feature
Description
IBM13M16734JCA is a registered 168-Pin Synchro-
nous DRAM Dual In-Line Memory Module (DIMM)
organized as a 16Mx72 high-speed memory array.
The DIMM uses nine 16Mx8 SDRAMs in 400 mil
TSOP packages. The DIMM achieves high-speed
data-transfer rates of up to 100 MHz by employing a
prefetch/pipeline hybrid architecture that synchro-
nizes the output data to a system clock.
The DIMM is intended for use in applications oper-
ating from 66MHz to 100 MHz, PC100, memory bus
speeds, and/or heavily loaded bus applications. All
control and address signals are re-driven through
registers/buffers to the SDRAM devices. The DIMM
can be operated in either registered mode (REGE
pin tied high), where the control/address input sig-
nals are latched in the register on one rising clock
edge and sent to the SDRAM devices on the follow-
ing rising clock edge (data access is delayed by one
clock), or in buffered mode (REGE pin tied low)
where the input signals pass through the regis-
ter/buffer to the SDRAM devices on the same clock.
XTK simulation models of the DIMM are available to
determine which mode to design for.
A phase-lock loop (PLL) on the DIMM is used to re-
drive the clock signals to the SDRAM devices to
minimize system clock loading. (CK0 is connected
to the PLL, and CK1, CK2, and CK3 are terminated
on the DIMM.) A single clock enable (CKE0) con-
trols all devices on the DIMM, enabling the use of
SDRAM power-down modes.
Prior to any access operation, the device CAS
latency and burst type/length/operation type must
be programmed into the DIMM by address inputs
A0-A9, A11, BS1 and BA1 using the mode register
set cycle. The DIMM CAS latency when operated in
buffered mode is the same as the device CAS
latency as specified in the SPD EEPROM. The
DIMM CAS latency when operated in registered
mode is one clock later due to the address and con-
trol signals being clocked to the SDRAM devices.
The DIMM uses serial presence detects imple-
mented via a serial EEPROM using the two-pin IIC
protocol. The first 128 bytes of serial PD data are
programmed and locked by the DIMM manufac-
turer. The last 128 bytes are available to the cus-
tomer and may be write protected by providing a
high level to pin 81 on the DIMM. An on-board pull-
down resistor keeps this in the write-enable mode.
All IBM 168-pin DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25" long space-saving
footprint.
06K2880.H01193
12/99
漏IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 1 of 20

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